We present an update of the AIS wavefront sensor, a diagnostic sensor set for insertion in the upgraded 0.5 NA SEMATECH Albany and Berkeley METs. AIS works by using offset monopole illumination to probe localized regions of the test optic pupil. Variations in curvature manifest as focus shifts, which are measured using a photodiode- based grating-on- grating contrast monitor, and the wavefront aberrations are reconstructed using a least-squares approach. We present results from an optical prototype of AIS demonstrating an accuracy of better than λ/30 rms for Zernike polynomials Z4 through Z10. We also discuss integration strategies and requirements as well as specifications on system alignment.
We present a simulation study of the near-field Extreme Ultraviolet (EUV) imaging technique to break the diffraction limit of conventional lithography for spatial frequency multiplication. Rigorous electromagnetic simulations are performed to investigate the near-field EUV imaging performance and its process capability. An optical index, depth of thickness fluctuation (DOT) is defined to characterize the tolerable variation of the imaging-layer thickness, which plays a key role in evaluating the feasibility of this lithography technology. High sensitivity of the near-field image (profile and amplitude) to both absorber CD and propagation depth is found in transverse-electric (TE) and transverse-magnetic (TM) illumination modes. Despite the attractive prospect of applying this near-field imaging technique for semiconductor manufacturing, technical challenges from its optical performance and process control are non-trivial.
We present a new form of optical testing for exposure tools based on measuring localized wavefront curvature. In this method, offset monopole illumination is used to probe localized regions of the test optic pupil. Variations in curvature manifest as focus shifts, which are measured using a photodiode-based grating-on-grating contrast monitor, and the wavefront aberrations are reconstructed using a least-squares approach. This technique is attractive as it is independent of the numerical aperture of the system and does not require a CCD or a separate interferometer branch.
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
Extreme ultra-violet Lithography (EUVL) alternating phase shift mask (APSM) or other optical enhancement
techniques are likely needed for 16nm (half pitch) technology generation and beyond. One possible option is the
combination of EUVL and APSM. The fabrication of EUVL APSM is more difficult than either the fabrication of an
EUVL binary mask or a conventional optical APSM mask. In the case of EUVL APSM, the phase difference in the
two regions (0 and 180-degree phase regions) is created by a phase step in the substrate prior to the multilayer (ML)
coating. The step height that induces 180-degree phase mismatch in the ML is determined by [λ/(4cosθ)](2m+1),
where m are integers (0, 1, 2,...). In this experiment, we targeted for a step height with m=1. The same mask design
also contains the standard binary structures so that the comparison between the EUVL APSM and the EUVL binary
mask can be performed under the same illumination and wafer process conditions. The EUVL APSM mask was
exposed using Nikon's EUV1 scanner in Kumagaya Japan. The wafer level results showed higher dense line
resolution for EUVL APSM as compared to that of EUVL binary mask. APSM also showed improved line width
roughness (LWR) and depth of focus (DoF) as compared to the best EUVL binary results obtained with C-dipole
off-axis illumination (OAI). The wafer CD resolution improvement obtained by APSM in this experiment is
partially limited by the resist resolution and the mask phase edge spread during ML deposition. We believe that
wafer CD resolution and can further be improved with imaging imbalance compensation mask design and
improvements in resist resolution and the phase generation portion of the mask fabrication process. In this paper, we
will discuss in detail the mask fabrication process, wafer level data analysis, and our understanding of EUVL APSM
Since its installment in 2004, Intel's extreme ultraviolet (EUV) micro-exposure tool (MET) has demonstrated significant
improvements in ultimate resolution capability. Initially capable of printing 45nm half-pitch (HP) lines with a 160nm
depth of focus (DOF), it is now capable of printing 22nm HP lines with up to a 275nm DOF and demonstrating
modulation down to 18nm HP. Initial improvements in resolution have been chiefly attributable to the maturation of
EUV masks and photoresists. Recent improvements that have enabled the 22nm HP imaging with a sizeable process
window are largely due to new illumination options that have become available as a result of recent tool upgrades. In
particular, the installation of a new nested Wolter collector with an additional outer shell that extended the maximum
partial coherence (σ) from 0.55 to 0.68, in conjunction with an updated pupil wheel and apertures, has enabled new
rotated quadrapole and on-axis dipole illumination settings with 0.36 inner σ and 0.68 outer σ. Here we present simulated
contrast curves alongside the experimental imaging results for the Intel MET using the newly available quadrapole and
on-axis dipole illumination settings and discuss our future plans for continued improvements to the Intel MET aerial image.
In this paper we present analytical and simulation results on the wafer-scan induced image blur and its impact on CD control, image slope and line-edge roughness (LER), and process window in maskless lithography. It is shown that the effects of image blur do not impose serious constraints on lithographic performance in low throughput operation. However, when throughput is high, significant CD enlargement, lower image slope and higher LER, and process window degradation are observed consistently in both coherent imaging analysis and partially coherent lithographic simulations. The dependence of CDs on the wafer's scan speed and the distance between neighboring features will be an important issue of maskless OPC development. We also analyze the potential challenges of image blur to DUV and EUV maskless lithography and propose several solutions to overcome them.
The absence of a reliable non-removable pellicle is a significant obstacle in the development of EUV lithography. In this paper we present analytical and experimental results of a pellicle concept. The concept is based on the development of an EUV transmissive film supported with a wire-mesh. The form factor of the proposed solution is not different from a standard pellicle application, thus this would not require dramatic tool design changes. Results from developmental studies of two materials, silicon (Si) and ruthenium (Ru), are presented. As expected, Si shows oxidation on both surfaces of the thin film, while the less transmissive Ru has excellent resistance to oxidation. Spectral analysis at EUV wavelengths of pellicle coupons agrees very well with the theoretical analysis.
EUV lithographic tools can support the 32 nm MPU manufacturing node and beyond. In order to meet the stringent requirements on CD control and overlay for such technology generations, wavefront error and flare of the EUV exposure systems have to be well controlled. The cross field variations of wavefront errors and flare need to be in the acceptable range in order to improve the common Depth of Focus (DoF) across the field. The impacts of lens aberration and flare to the aerial image at the system level are studied for the 32nm MPU technology node using Intel's aerial image simulation tool. The focus control budget of the exposure tools has been estimated. Useable Depth of Focus (UDoF) has been defined, and focus margin between UDoF and focus control budget from the exposure tool has been calculated for various cases. Focus margin has been used to determine the flare and lens aberration requirements for the 32nm MPU node. It is found that <10% intrinsic flare and <0.75nm rms lens aberration are required for the 32nm MPU node. Process window as a measure of individual aberration terms for the 32nm node has been also investigated.
In this paper we present the design and fabrication results of tilting and piston micromirrors for their potential applications in DUV and EUV maskless lithography. The dynamic characteristics such as stability, damping, and the settling time of various types of electro-mechanically coupled micromirrors are investigated using the perturbation method, linear control theory, and numerical simulation. Non-dimensional control parameters are identified and transient optimization is carried out to minimize the systems’ settling time. It is found that vertical double-comb tilting micromirrors and clamped double-flexure piston micromirrors have superior stability.
The mirror hinge is proposed to function as a built-in resistor to introduce optimal electrical damping for EUV micromirrors operating in vacuum. We have developed a low-temperature (<420°C) IC compatible SiGe process, in which SiGe can be doped at different levels without annealing to function as a structural (conductive) and damping (resistive) material. Self-aligned processes using "spacer nanolithography" to define ultra-thin nano-scale actuation gaps for low-voltage operation have been developed to fabricate both tilting and piston micromirrors. We have successfully constructed double-comb tilting micromirrors with 300-nm fingers and 40-nm finger gaps, and double-flexure piston micromirrors with 80-nm thick flexures and 80-nm actuation gaps. The mirror sizes are in the range of 10 to 0.5 mm.
This paper discusses image optimization challenges posed by a mirror based pattern generation scheme. We address defocus related image drift encountered with mirror based maskless lithography. While off-grid contacts printed with piston mirrors are most severely affected most other features can be printed with minimum loss of telecentricity. A novel double-piston mirror architecture based on a combination of tilting and piston mirrors is introduced. It operates as a pseudo-tilt mirror but also has the advantage of allowing strong phase-edges due to pure-phase wavefront modulation. Exposure latitude versus depth-of-focus process window curves of typical features show that the new mirror design behaves as well as tilting mirror. An image optimization algorithm is presented that iteratively updates the mirror array phase-map to optimally print dense layout, accounting for inter and intra feature proximity effects.
Future maskless lithography systems require data throughputs of the order of tens of terabits per second in order to have comparable performance to today’s mask-based lithography systems. This work presents an approach to overcome the throughput problem by compressing the layout data and decompressing it on the chip that interfaces to the writers. To achieve the required throughput, many decompression paths have to operate in parallel. The concept is demonstrated by designing an interface chip for layout decompression, consisting of a Huffman decoder and a Lempel-Ziv systolic decompressor. The 5.5mm x 2.5mm prototype chip, implemented in a 0.18μm, 1.8V CMOS process is fully functional at 100MHz dissipating 30mW per decompression row. By scaling the chip size up and implementing it in a 65nm technology, the decompressed data throughput required for writing 60 wafers per hour in 45nm technology is feasible.
We study mirror based pattern generation systems to provide an understanding of how they can be operated in an analog mode to meet the quasi-continuous sizing and placement requirements of optical lithography. Both tilting mirrors and piston-motion mirrors are examined. The aerial images are compared with those generated by simple binary masks. The effect of grayscaling, used to place and size features, on image quality is measured. Normalized image log slope (NILS) is used as the measure of image quality. Tilting mirrors used in grayscale mode provide image quality comparable to binary masks, and piston mirrors are somewhat better.