Strong resolution enhancement technologies (RETs) combined with hyper-NA
ArF immersion lithography with source and mask optimization (SMO) have become
necessary to achieve sufficient resolution in 2Xnm node devices. Conventional SMO
methods have focused on minimizing the edge placement error and/or the cost functions
of dose, focus, and mask errors. This has not, however, resolved the conflict between line
and gap patterns on logic gate layouts. One issue remaining in particular is the mask error
enhancement factor (MEEF). Furthermore, the pattern shapes at the line end gaps of
SRAM gates remain a major challenge for logic device manufacturers. To overcome
these problems, we explain the importance of controlling the light intensity profiles at
line end gaps, focusing on a Panasonic product called "Mask Enhancer" that comprises
an attenuated mask with a phase shifting aperture and enables light intensity profiles to be
controlled easily. We demonstrate the product's effectiveness in printing gates with
optimized illumination source shapes. A simulation experiment and a feasibility study
confirmed that Mask Enhancer can improve the MEEF and pattern shapes at the line ends
of SRAM gates.
We have proposed a methodology for 130-nm DRAM patterning. We started by running a simulation to investigate the possibility of 130-nm DRAM production with KrF lithography. We optimized cell array features and isolate lines in the core circuits and peripheral circuits, corresponding to resist performance ((Delta) L). Using a half-tone phase-shift mask, off-axis illumination, and 0.68-NA KrF scanner, we found a high-performance resist of 40-nm (Delta) L that meets the requirement. Then, we screened resist samples using design of experiment. The result was a 40-nm (Delta) L positive resist that has small line edge roughness, a high- contrast resist profile, a small iso-dense bias and a low- blocking level to prevent defects. Finally, we applied this positive resist and OPC-mask to critical layers and achieved a sufficient production margin using a 0.68-NA KrF scanner.
We studied the use of attenuated phase shift mask (PSM) in DRAM production. There exists several problems with the use of an attenuated PSM compared to a conventional Cr mask. These include a need to form an opaque region, facilitate reticle alignment with a stepper, and optimize mask bias to prevent side peak printing. First, we investigated the characteristics of checkerboard patterns in achieving an opaque region. We confirmed the feasibility of making a mask to maintain opaqueness. Next we developed a mask fabrication process so to enable reticle alignment in some kinds of steppers by using an additional Cr layer under the attenuated layer. Finally, we tried to implement attenuated PSM in a previous generation stepper. We found that we must pay attention to lens aberration when optimizing mask bias.
A phase-shifting technique which simplifies mask fabrication and is applicable to actual IC patterns has been introduced into the i-line positive resist process. It combines edge-contrast enhancement and a chromeless mask. Although the effect of this technique on line and space patterns has turned out to be more restricted than that of the alternating mask technique, it can improve exposure and focus latitude in isolated hole patterning. The authors report on their estimation of the optimum shifter width which maximizes contrast enhancement on lines and spaces as well as on isolated hole patterns. Experimental data is presented to verify the improvements in photolithographic performance of isolated hole patterning due to this technique.
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