Suboptimal layout geometries after optical proximity correction (OPC) might induce lithography hotspot, and result in degradation of wafer yield during integrated circuit (IC) manufacturing. Conventional hotspot correction methods have been widely conducted on post-OPC layout, such as rule-based or model-based hotspot fixing, but these methods might not completely solve hotspot issues due to the time-consuming process or model inaccuracy. Over the past of few years, the explosive growth of machine learning techniques has boosted the capability of computational lithography including hotspot detection and correction. In this paper, we focus on lithography hotspot correction with Generative Adversarial Network (GAN) to modify pattern shapes of hotspot and further improve lithographic printing of designed layout. The proposed approach first built a hotspot correction model based on different types of lithography rule check (LRC) hotspots, by training a pix2pix model to learn the correspondences between paired post-OPC layout image and after development inspection (ADI) contour image simulated from LRC tool. Then, we input hotspot-free contour image created from original hotspot into the deep learning model to generate supposedly hotspot-free mask image, and converted the mask image back into polygonal layout. Finally, mask layout with hotspot were partially replaced with predicted mask layout, and then examined with LRC simulation. Furthermore, we also implemented transfer learning for new hotspots captured from new design layout to expand the capability of our hotspot correction flow. Experimental results showed that this methodology successfully corrected lithography hotspots and significantly enhanced the efficiency of hotspot correction.
BackgroundAlgorithmic breakthroughs in machine learning (ML) have allowed increasingly more applications developed for computational lithography, gradually shifting focus from hotspot detection to inverse lithography and optical proximity correction (OPC). We proposed a pixelated mask synthesis method utilizing deep-learning techniques, to generate after-development-inspection (ADI) contour and mask feature generation.AimConventional OPC correction consists of two parts, the simulation model which predicts the expected contour signal, and the correction script that modifies the actual layout. With practicality in mind, we collected modeling wafer data from scratch, then implemented ML models to reproduce conventional OPC actions, mask to contour prediction, and design to mask correction.ApproachTwo generative adversarial networks (GANs) were constructed, a pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer. The second model is embedded into machine learning mask correction (ML-OPC) framework, output mask is optimized through minimizing pixel difference between design target and simulated contour.ResultsTwo different magnification SEM image datasets were collected and studied, with the higher magnification showing better simulator pixel accuracy. Supervised training of the correction model provided a quick prototype mask synthesis generator, and combination of unsupervised training allowed mask pattern synthetization from any given design layout.ConclusionsThe experimental results demonstrated that our ML-OPC framework was able to mimic conventional OPC model in producing exquisite mask patterns and contours. This ML-OPC framework could be implemented across full chip layout.
With the algorithmic breakthroughs in machine learning, increasingly more applications have been developed for computational lithography. In this paper, a pixelated mask synthesis method including After Development Inspection (ADI) contour and mask feature generation, was proposed by utilizing deep learning technique. Two Generative Adversarial Networks (GANs) were constructed, the first network was for mask to contour prediction, and the consecutive network was to perform design to mask correction. A pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer, thus the capability of printing prediction can be established. The well trained mask-to-contour model was then implemented as the simulator component of machine learning mask correction (ML-OPC) framework. Next, another unsupervised GAN formed the front-end of ML-OPC framework to synthesize mask patterns from any given design layout. Generated mask patterns were eventually optimized through minimizing pixel difference between design target and corresponding contour generated by mask-to-contour model. The experimental results demonstrated that our ML-OPC framework can mimic conventional OPC model to produce exquisite mask patterns and contours.
As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique (RET) applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have been widely adopted. The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs, but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better process window as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. In this paper, generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check (MRC) constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon Source-Mask Optimizer (SMO). Most importantly, the efficiency of SRAF insertion can be enhanced significantly through the generative adversarial network.
This work compared the CD-based and image-assistant approaches for calibrating the OPC models. OPC models were
first developed for 65nm-node memory contact layer and calibrated by contact test patterns with various ellipticities. The
image-assistant model is a hybrid one calibrated by SEM contours and 1D measurement results, while the CD-based
model calibration uses 1D measurement results as the sole data source. The fitting errors, model prediction ability and
OPCed results were compared between these two models. Besides, the challenges on calibrating the edge-detection
algorithm of the CD SEM images to the extracted contours of OPC tool were also discussed. Finally, the layouts
corrected by CD-based and image-assistant models were written on a test mask for wafer-level comparison.
The results displayed that the CD-based model showed smaller error on fitting and interpolation, but image-assistant
model got improvement on extrapolation prediction of array-edge contact, unknown contact pattern and long contacts.
The wafer-level comparison also revealed the image-assistant model outperformed to the CD-based model by smaller
correction error on unexpected patterns.
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