Dr. Yong-Dong Wang Profile

Dr. Yong-Dong Wang

Sr. Director, Product Engineering at Synopsys Inc

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Publications (9)

Proceedings Article | 22 November 2023 Presentation

ML-model based curvilinear mask error correction

Linghui Wu, John Valadez, Jian Rao, Jim Burdorf, Yunqiang Zhang, Yongdong Wang, Alex Zepka, Folarin Latinwo

Proceedings Volume PC12751, PC1275109 (2023) https://doi.org/10.1117/12.2687654

KEYWORDS: Error control coding, Performance modeling, Resolution enhancement technologies, Printing, Optical proximity correction, Model-based design, Manufacturing, Extreme ultraviolet, Convection

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Proceedings Article | 21 November 2023 Presentation + Paper

Curvilinear OPC mask synthesis flow

Yunqiang Zhang, Linghui Wu, Jian Rao, Yongdong Wang

Proceedings Volume 12751, 127510T (2023) https://doi.org/10.1117/12.2686921

KEYWORDS: Optical proximity correction, Extreme ultraviolet

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Proceedings Article | 28 April 2023 Presentation + Paper

Scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis

Jun Zhu, Lin Wang, Brad Falch, Thuc Dam, Yongdong Wang, Petrisor Panaite, Mingchao Ji, Yuan Yuan Li, Ming Su

Proceedings Volume 12495, 124950X (2023) https://doi.org/10.1117/12.2662031

KEYWORDS: Design and modelling, Resolution enhancement technologies, Manufacturing, Lithography, Source mask optimization, Reconstruction algorithms, Printing, Yield improvement, Visual inspection, Very large scale integration

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For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.

Proceedings Article | 28 April 2023 Presentation + Paper

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Jennefir Digaum, Gary Chiang, Lin Wang, Kyle Braam, Dave Gerold, Yongdong Wang, Thuc Dam

Proceedings Volume 12495, 1249503 (2023) https://doi.org/10.1117/12.2657538

KEYWORDS: Design and modelling, Optical proximity correction, Semiconducting wafers, Lithography, Manufacturing, Visualization, Reticles, Printing, 193nm lithography, Source mask optimization

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Proceedings Article | 23 March 2020 Paper

Impact of flare on source mask optimization in EUVL for 7nm technology node

Lisong Dong, Rui Chen, Taian Fan, Rongbo Zhao, Yayi Wei, Jianjun Jia, Zac Levinson, Thuc Dam, Jay Lee, Yongdong Wang, Larry Melvin

Proceedings Volume 11323, 113232E (2020) https://doi.org/10.1117/12.2552008

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Source mask optimization, Nanoimprint lithography, Lithography, Extreme ultraviolet, Electroluminescence, Reflectivity, Critical dimension metrology, Light scattering

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Proceedings Article | 16 March 2009 Paper

Efficient hardware usage in the mask tapeout flow

Mathias Boman, Travis Brist, Yongdong Wang

Proceedings Volume 7274, 72742H (2009) https://doi.org/10.1117/12.815019

KEYWORDS: Optical proximity correction, Computed tomography, Photomasks, Electroluminescence, Lithium, Electronic design automation, Data processing, Manufacturing, Logic

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Proceedings Article | 31 October 2007 Paper

Improvements in model-based assist feature placement algorithms

Benjamin Painter, Levi Barnes, Jeffrey Mayhew, Yongdong Wang

Proceedings Volume 6730, 67304Y (2007) https://doi.org/10.1117/12.746702

KEYWORDS: Model-based design, Atrial fibrillation, Optical proximity correction, Systems modeling, Image processing, Photomasks, Process modeling, System on a chip, Optical components, Image resolution

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Proceedings Article | 27 January 2005 Paper

Increasing post OPC layout verification coverage using a full-chip simulation based verification method

Chi-Yuan Hung, Yong Dong Wang, Ze Xi Deng, Gen Sheng Gao, Ming Hui Fan

Proceedings Volume 5645, (2005) https://doi.org/10.1117/12.572711

KEYWORDS: Optical proximity correction, Resolution enhancement technologies, Photomasks, Semiconducting wafers, Process modeling, Lithography, Bridges, Reticles, Design for manufacturing, Silicon

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Proceedings Article | 6 December 2004 Paper

Formation and verification of a 90-nm contact lumped model

Chi-Yuan Hung, Bin Zhang, Yong Done Wang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569308

KEYWORDS: Data modeling, Optical proximity correction, Etching, Semiconducting wafers, Photomasks, Optical lithography, Wafer-level optics, Model-based design, Photoresist processing, Resolution enhancement technologies

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Showing 5 of 9 publications

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