In the manufacture of devices beyond the 45 nm node, it is important to employ a high-performance multi-layer resist (MLR) process that uses silicon containing ARC (Si-ARC) and spin on carbon (SOC). We examined an additional hardening process of SOC by H2 plasma treatment in order to improve the etching durability of the MLR. The dry etching durability of H2-plasma-hardened SOC film showed a drastic improvement, while the wiggling features of the MLR without H2 treatment observed after SiO2 etching disappeared completely. The hardening mechanism of SOC was analyzed by Fourier transform infrared spectroscopy (FTIR) with gradient shaving preparation (GSP) and Raman spectrometry. The formation of diamond-like amorphous carbon at a depth of approximately 50 nm was observed and was attributed to the improvement in the dry etching durability. In addition, the MLR stack with hardening has good reflectivity characteristics. The simulated reflectivity at the interface between the bottom of the resist and top surface of the MLR stack with hardening below 0.6% was attained over a wide range of Si-ARC thicknesses and hyper NA (~1.3) regions. The measured refractive indices of the hardened SOC film at 193 nm had a high value at the surface; however, they gradually decreased toward the inner region and finally became the same as those of untreated SOC. This might be the origin of the estimated excellent reflectivity characteristics.
A novel process of OPC-free on-grid fine random hole pattern formation is developed. Any random hole pattern with
~120nm diameter on 240 nm base grid can be printed by KrF exposure. In this technique, double resist patterning
scheme is adopted. Dense hole pattern is delineated with first resist process. Quadrupole illumination is applied with
embedded attenuating phase shift mask (EA-PSM) in imaging on this step. As is well known, fine dense hole pattern
is formed with very large process latitude. After development of the first resist, hardening of the resist film by Ar ion
implantation is carried out so as not to mix with second resist at second coating. This hardening process is very robust
such that rework in second resist process can be performed with stripping the resist by a solvent. Then, second resist
patterning is carried out. In the second exposure, cross-pole illumination is applied with high transmission EA-PSM.
By this imaging, very fine dark spot image is generated. Resultantly, fine random pillar patterns, which plug an
underlying hole, are formed in the second resist film. Because function of the pillar is plugging a hole, no precise CD
control is required. Moreover, pattern connection between adjacent pillars does not cause any problem. Hence, no
OPC is needed in the pillar formation, regardless of printed size variation of the pillars. Undesired holes in the dense
holes are plugged by the pillars. As a result of the double resist patterning, on-grid random hole pattern is successfully
delineated. Due to the robustness of each patterning process, very high process latitude is achieved. Off course, this
technique can be carried out under any wavelength on regard of imaging. In other aspect, this technique utilizes only
positive-tone resist. Hence, this technique can be applied with leading-edge ArF immersion lithography. As a
conclusion, this technique is a promising candidate of hole pattern formation in 32nm era and beyond.
As a promising way to scale down semiconductor devices, 193-nm immersion exposure lithography is being developed
at a rapid pace and is nearing application to mass production. This technology allows the design of projection lens with
higher numerical aperture (NA) by filling the space between the projection lens and the silicon wafer with a liquid
(de-ionized water). However, direct contact between the resist film and water during exposure creates a number of
process risks. There are still many unresolved issues and many problems to be solved concerning defects that arise in
193-nm immersion lithography.
The use of de-ionized water during the exposure process in 193-nm immersion lithography can lead to a variety of
problems. For example, the trapping of microscopic air bubbles can degrade resolution, and residual water droplets left
on the wafer surface after immersion exposure can affect resolution in the regions under those droplets. It has also been
reported that the immersion of resist film in de-ionized water during exposure can cause moisture to penetrate the resist
film and dissolve resist components, and that immersion can affect critical dimensions as well as generate defects.
The use of a top coat is viewed as one possible way to prevent adverse effects from the immersion of resist in water, but
it has been reported that the same problems may occur even with a top coat and that additional problems may be
generated, such as the creation of development residues due to the mixing of top coat and resist. To make 193-nm
immersion lithography technology practical for mass production, it is essential that the above defect problems be solved.
Importance must be attached to understanding the conditions that give rise to residual defects and their transference in
the steps between lithography and the etching/cleaning processes.
In this paper, we use 193-nm immersion lithography equipment to examine the transference (traceability) of defects that
appear in actual device manufacturing. It will be shown that defect transfer to the etching process can be significantly
reduced by the appropriate use of defect-reduction techniques.
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