We have proposed the cost model of advanced mask and calculated the cost of advanced mask as the ratio for the 152 mm, 5x reticle cost of 64MDRAM, 0.35 micrometers design rule. The 152 mm, 5x reticle cost of 256MDRAM, 0.25 micrometers design rule is 1.6 times higher. The 152 mm, 4x reticle cost of 1GDRAM, 0.18 micrometers design rule is 3.5 times higher. The 230 mm, 4x reticle cost of 4GDRAM, 0.13 micrometers design rule is seven times higher. The reticle cost increases rapidly with each generation. Based on the calculated results of the reticle cost, we have calculated the CoO of advanced optical lithography, and compared it with those in E-beam and x-ray lithography. The cost of optical lithography is the cheapest throughout the generation, assuming the reticle lifetime of more than 1350 wafers. However, the cost of optical lithography becomes more expensive if we assume the reticle lifetime of less than 800 wafers in 0.13 micrometers design rule and 1350 wafers in 0.18 micrometers design rule, respectively.
We report here survey and discussion results on mask accuracy and mask size at the 1995 PMJ (Photomask Japan) Rump Session. The questionnaires consist of mask size, lithography error budget, and mask error budget for 64M DRAM, 256M DRAM, and 1G DRAM. The number of replies was 52, 26 in advance and 26 on site. Seven panelists presented short papers on mask accuracy from the technical fields of device, lithography, mask making, and mask- related equipment. The discussion results of panelists also are shown.
The optimized design and fabrication of optical proximity correction (OPC) masks with serifs have been described for the application of mask ROM programming layer, which has 1 micrometers square patterns with 0.6 micrometers separation on a g-line stepper with 0.45 numerical aperture (NA). We have optimized the trade-off among the optical correction effects, practical mask fabrication problems, and inspection problems. Firstly, to obtain the sufficient correction effect on the topographic substrate, we have executed not only the simulation and experiments on the flat substrate, but also the experiments on the topographic substrate. Secondly, from the practical mask fabrication considerations we fixed the rules that the size of serifs must be larger than 1.0 micrometers square and the minimum separation width of mask patterns must be larger than 1.5 micrometers on 5X reticle. Thirdly, to maximize the detection capability of mask defects and to minimize the detection of false defects, we have fitted the fabricated mask patterns to the designed data by optimizing the electron dose.
An application of a mask with serif patterns to a 0.8 micrometers rule mask ROM programming layer is discussed. A serif pattern is the unprinting size pattern added to the corner of original pattern. It suppresses the corner rounding caused by the lack of resolution performance of a lithography exposure system. We aimed to make 1.0 micrometers square pattern with g-line (436 nm). There are some difficulties in application of optical proximity correction (OPC) mask. One of the problems is the optimization of the mask design to be applied to get the appropriate correction effect. We evaluated it by simulation and experiment. The second is the increase in EB data volume. We split mask data into periodic common data with serifs for cell pattern and random ROM code data for programming to compact the data volume. The other is the printability and inspection of mask defects. The OPC mask shows the high printability of defects because of the violation of the mask design. To detect all the printable defects, mask inspection needs high sensitivity. In the inspection with high sensitivity, the extrusion of pattern caused by EB proximity effect becomes to be detected as false defect. To reduce the false defects, we optimized the EB exposure process. In order to use the OPC masks in actual production, mask design for application should be optimized not only in the viewpoint of pattern correction effect but also in the viewpoint of mask fabrication and inspection.
The lithographic performance and process applicability of the anti-reflective-layer (ARL) process using amorphous carbon have been studied in i-line and KrF excimer laser lithography. The ARL thickness of 30 nm was used. With ARL, the reflectivity from the silicon substrate reduced to less than 30%. The reduction of the reflectivity with ARL process was effective not only for the silicon substrate but also for the tungsten silicide substrate and aluminum substrate. The pattern profile and depth of focus in the resist on ARL were almost the same as those without ARL. The ARL process has been successfully applied for the fabrication of 0.35 micrometers CMOS polycide gate fabrication using i-line lithography and 0.35 micrometers DRAM aluminum wiring using excimer laser lithography.
We have investigated the application of phase-shifting mask (PSM) or DRAM cell capacitor fabrication. Narrow spaces formed by PSM enables us to attain a high DRAM cell capacitance. Four types of phase-shifting masks are tested: a rim-type mask, transparent type mask (I) (or `shifter-shutter' type), Levenson type mask and transparent type mask (II) (or `shifter-edge' type). The improvement in resolution and depth-of-focus (DOF) by the former two types of PSMs is small, although we can continue to use conventional positive resist with these PSMs. The latter two PSMs provide a significant increase in resolution and DOF. Since the transparent type (II) mask has the difficulty in mask fabrication, we select a Levenson type PSM for the fabrication of the DRAM cell capacitor. Though 0.28 micrometers spaces with the DOF of 1.5 micrometers can be formed on a bare silicon substrate by the Levenson type PSM, the printed patterns on an actual device substrate are deformed by the reflection from the substrate. Dyed negative resist is used to reduce the effects of the reflection, the patterns of 0.28 micrometers spaces with 0.6 micrometers DOF on the actual substrate can be successfully printed. We confirm the effectiveness of the Levenson type phase-shifting mask combined with a dyed negative resist for the DRAM cell capacitor fabrication.
We report here survey results on pattern dimension measurement of masks and wafers. The SEMI Standard Metrology Committee in Japan have carried out a survey from June to September in 1992. The target of this survey consists of semiconductor device makers, inspection equipment makers, material makers, and academic institutes. We have got replies for ten questions from 44 respondents, and found some interesting results. E(Electron)-beam and optical equipment are mainly used in the R&D and the mass production lines respectively. In appears that the e-beam equipment is gradually replacing the optical equipment as a tool to measure finer pattern dimensions, however the e-beam equipment still has problems, like the measurement of contact-holes, or the assurance of the measurement accuracy which corresponds to the expected patterns' dimension. On the other hand, more than 2/3 of respondents have replied that they would like to standardize the measurement method itself in order to transfer process technologies from R&D to the mass production lines, or to make more flexible production lines, and about 85% of them have replied concerning the necessity of measuring finer pattern dimension absolutely to keep a common scale.
Wafer charging in barrel etchers, reactive ion etching (RIE) etchers, magnetron RIE (MRIE) etchers and electron cyclotron resonance (ECR) etchers are characterized. The charging voltages were measured by using electrically programmable non-volatile memories. The charging profile for the barrel etchers and the RIE etcher depends critically on the electrode arrangements and wafer locations, while that in the MRIE etchers and the ECR etchers depends on the structure of the magnetic field. Even in the case of a non-divergent magnetic field ECR etcher, wafer charging is built-up when an RF bias is applied to the wafer stage.
By analyzing these results, two charging mechanisms are distinguished. One is the plasma nonuniformity around the wafer, which depends on the RF electrode and the wafer location. The other is the anisotropy of the magnetized plasma, which depends on the structure of the magnetic field. Some of the charging profiles due to the former effect is reproduced by using an equivalent circuit model. It is found from the model that even in the uniform density plasma, wafer charging is induced by the RF current which causes a plasma potential variation across the wafer surface.
This paper introduces the novel concepts of 'multistage phase shifter' and 'comb-shaped shifter' for resolving the problems of a transparent type phase shifting mask. The use of a multistage shifter decreases the light intensity dip at the shifter edges. The use of the comb- shaped shifter enables control of the pattern width. The effectiveness of a multistage shifter and a comb-shaped shifter were demonstrated by experiments and simulations. These technologies make it possible to fabricate a wide range of patterns for VLSI using the transparent phase shifting mask.
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