A novel surface plasmon resonance (SPR) sensor system using CMOS image sensor array is proposed in this paper. Recently, a simple SPR system was proposed by the author, which achieved high resolution and fast response time using a bi-cell photo-detector. However it requires mechanical adjustment process to balance two signals of the bi-cell before measurement. It requires not only additional time but also additional mechanical control unit, which is a source of the noise. It also suffers from the small linear range. The proposed method chooses a pixel as the center from many pixels, which gives the most balance of bi-cell signal. Therefore no mechanical adjustment is required. The method also overcomes the small linear range problem by switching the center adaptively during the test. Furthermore, it has several advantages of CMOS image sensor such as low cost, low power, and on-chip functionality, which makes the proposed SPR sensor system be a good candidate for field applications. A prototype CMOS image sensor chip with 12bits analog to digital converter is designed and fabricated with 0.5um AMI CMOS technology.
In these days, the CMOS image sensors are commonly used in many low resolution applications because the CMOS
imaging system has several advantages against the conventional CCD imaging system. However, there are still several
problems for the realization of the single-chip CMOS imaging system. One main problem is the substrate coupling
noise, which is caused by the digital switching noise. Because the CMOS image sensors share the same substrate with
surrounding digital circuit, it is difficult for the CMOS image sensor to get a good performance. In order to investigate
the substrate coupling noise effect of the CMOS image sensor, the conventional CMOS logic, C-CBL
(Complementary-Current balanced logic) and proposed low switching noise logic are simulated and compared.
Consequently, the proposed logic compensates not only the large digital switching noise of conventional CMOS logic
,but also the huge power consumption of the C-CBL. Both the total instantaneous current behaviors on the power
supply and the peak-to-peak voltages of the substrate voltage variation (di/dt noise) are investigated. The simulation is
performed by AMI 0.5μm CMOS technology.
A CMOS focal-plane-array is designed for the high-throughput analysis of enzymatic reaction in on-chip spectrophotometer system. One of potential applications of the presented prototype system is to perform enzymatic analysis of biocompounds contained in blood. This function normally requires an expensive diode-array spectrophotometer, but it is possible to perform high throughput analysis with low budget if the spectrophotometer system is scaled down to a chip. The CMOS active pixel sensor array can cover a layer of polydimethylsiloxane (PDMS) forming the microfluidic channels and the substrate solution for enzymatic reaction can be injected into the channels by capillary force. Under room light, the underneath CMOS active pixel sensor with 40 x 40 pixels detect the gray levels of the fluid’s color. Inside the image sensor chip (size: 3mm x 3mm), the pixels of the same column share the same sample and hold circuits. The analog signals from 40 columns are multiplexed into one input feeding an on-chip 8 bits dual-slope analog to digital converter. The color change can be displayed on the external monitor by using a data acquisition card and personal computer.
CMOS image sensors have several clear advantages over CCD image sensors: selective readout, low power, small size, high frame rate, on-chip functionality, and low cost. However CCD image system still dominates over digital camera market, because the CMOS image system has a poor dynamic range and peak signal-to-noise ratio. In this paper, we propose a new enhanced DR and SNR CMOS image sensor with pixel parallel analog-to-digital converter (ADC) and memory. The proposed reset and time-to-digital converter (TDC) increase the well capacity of the image sensor. Consequently, DR and peak SNR are increased simultaneously while other DR enhancement schemes can't increase peak SNR. The circuit reuse concept is proposed to increase the fill factor. We designed and simulated the proposed circuit and achieved 12bit resolution with 1000frames/sec. Power consumption per each pixel is 50nW. DR is increased by 36dB and peak SNR is enhanced by 18dB.
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