As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after
optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by
k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination
(OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to
cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed -
contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate
false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important
thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole
wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check,
verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points
of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least.
In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of
CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with
neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through
the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient
verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase
efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is
As integrated circuit technology advances and features shrink, the scale of critical dimension (CD) variations induced by
lithography effects become comparable with the critical dimension of the design itself. At the same time, each
technology node requires tighter margins for errors introduced in the lithography process. Optical and process models --
the black boxes that simulate the pattern transfer onto silicon -- are becoming more and more concerned with those
different process errors. As a consequence, an optical proximity correction (OPC) model consists mainly of two parts; a
physical part dealing with the physics of light and its behavior through the lithographical patterning process, and an
empirical part to account for any process errors that might be introduced between writing the mask and sampling
measurements of patterns on wafer. Understanding how such errors can affect a model's stability and predictability, and
taking such errors into consideration while building a model, could actually help convergence, stability, and
predictability of the model when it comes to design patterns other than those used during model calibration and
verification. This paper explores one method to quickly enhance model accuracy and stability.
In microelectronics manufacturing, photolithography is the art of transferring pattern shapes printed on a mask to silicon
wafers by the use of special imaging systems. These imaging systems stopped reducing exposure wavelength at 193nm.
However, the industry demand for tighter design shapes and smaller structures on wafer has not stopped. To overcome
some of the restrictions associated with the photographic process, new methods for Resolution Enhancement Techniques
(RET) are being constantly explored and applied. An essential step in any RET method is Optical Proximity Correction
(OPC). In this process the edges of the target desired shapes are manipulated to compensate for light diffraction effects
and result in shapes on wafer as close as possible to the desired shapes. Manipulation of the shapes is always restricted
by Mask Rules Checks (MRCs). The MRCs are the rules that assure that the pattern coming out of OPC can be printed
on the mask without any catastrophic faults. Essential as they are, MRCs also place constrains on the solutions explored
by the OPC algorithms.
In this paper, an automated algorithm has been implemented to overcome MRC limitations to RET by decomposing the
original layout at the places where regular RET hit the MRC during OPC.This algorithm has been applied to test cases
where simulation results showed much better printability than the normal conventional solutions. This solution has also
been tested and verified on silicon.
Resolution enhancement technologies (RET), such as optical proximity correction (OPC) help us develop sub-
100nm technology node by using photolithography equipments and materials for 130nm photolithographic process.
Because the resolution of scanner and materials has arrived almost at their limit, small patterns below resolution limit are
more sensitively affected by very small tolerance of various factors which were not considered by major process
parameters such like lens flare, reticle haze, reticle critical dimensional (CD) errors, etc. As patterning small ones under
resolution limit directly means large MEEF (mask error enhancement factor) in photo process, reticle CD errors are
actually magnified on wafer. Therefore, reticle CD errors should be tightly controlled when we try to define small
patterns under resolution limit.
As the feature size shrinks down, the importance of OPC model accuracy grows up for the purpose of ensuring
high pattern fidelity. In conventional process of OPC model generation, we don't concern how mask database CDs are
exactly matched with real reticle CDs, since the specification of reticle CD is enough tight to ignore CD variation on the
reticle such as 1-dimensional CD difference, linearity CD uniformity. But in the process with large MEEF, OPC model
with incorrect CD information of reticle has a bad influence to prediction pattern fidelity.
In this paper, we describe the effect of reticle CD errors on the OPC model accuracy. To quantify that effect, we
compared two cases of OPC model generation. One is making OPC model by using mask database CDs themselves, the
other is by using mask real CDs in 110nm node for poly and metal 1 (damascene) layers. As a consequence of the test,
we can achieve the accuracy OPC model calibrated with reticle CD errors which better predicts wafer CDs and 2-
dimensional images than the model, calibrated by original database CDs.
The methodology of lithography friendly design (LFD) has been widely adopted since it dramatically reduces cycle of
design revision as well as number of learning cycles to reach acceptable yield. LFD is, for example, the reduction
number of small jogs and notches in original, pre-OPC layouts. We can call them as OPC-unfriendly patterns since they
create unnecessarily complicated OPC patterns. They usually meet design rule so that DRC does not detect or screen
them out. Also, they make many errors after OPC because OPC model recognizes just as one of small features that it
should care. This generates many false alarms at OPC verification and mask rule check.
General approach to implement LFD is to update rule table or design rule by taking actual yield and failure analysis
data into consideration of database handling flow. Another method is the utilization of simulation to predict lithography
unfriendly designs. It takes time to setup excellent rule for accurate prediction even if they are very good approach as
fundamental solution for LFD. It will be better to have a simple solution with fast setup and improvement on major
lithography unfriendly designs such as small jogs and notches.
In this paper, we proposed new type of LFD flow which is the application of modified DRC step on LFD flow. This
modified DRC identifies OPC-unfriendly patterns, and changes to "OPC-friendly" as well as fixing design rule
violations. It is a pre-OPC layout treatment to remove small jogs and notches. After finding small jogs or notches, DRC
software removes jogs and notches. In this case, unnecessary OPC fragments could be avoided. Using this jog-fill
technique, we can dramatically reduce the incidence of necking or bridging, improve contact coverage, and, as a result, it
enhances the final yield and reliability of circuit.