Proceedings Article | 23 March 2020
Yifei Lu, Yuhang Zhao, Ming Li, Wei Yuan, Xiang Peng, Hongmei Hu, Shuxin Yao, Zhunhua Liu, Yu Tian, Ying Gao, Bingyang Pan, Weijun Wang, Chunyan Yi, Jinze Wang, Qian Xie, Xichen Sheng, Ying-chen Wu, Guanyong Yan, Yanjun Xiao, Liang Liu, Liang Ji, Qian Zhao, Yongfa Fan, Yiqiong Zhao, Mu Feng, Yueliang Yao, Terrance Yang, Jun Lang
Proc. SPIE. 11327, Optical Microlithography XXXIII
KEYWORDS: Metrology, Data modeling, Calibration, Etching, Image processing, Scanning electron microscopy, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Performance modeling
The semiconductor design node shrinking requires tighter edge placement errors (EPE) budget. OPC error, as one major contributor of EPE budget, need to be reduced with better OPC model accuracy. In addition, the CD (Critical Dimension) shrinkage in advanced node heavily relies on the etch process. Therefore AEI (After Etch Inspection) metrology and modeling are important to provide accurate pattern correction and optimization. For nodes under 14nm, the etch bias (i.e. the bias between ADI (After Development Inspection) CD and AEI CD) could be -10 nm ~ -50 nm, with a strong loading and aspect-ratio dependency. Etch behavior in advanced node is very complicated and brings challenges to conventional rule based OPC correction. Therefore, accurate etch modeling becomes more and more important to make precise prediction of final complex shapes on wafer for OPC correction. In order to ensure the accuracy of etch modeling, high quality metrology is necessary to reduce random error and systematic measurement error. Moreover, CD gauges alone are not sufficient to capture all the effects of the etch process on different patterns. Edge placement (EP) gauges that accurately describe the contour shapes at various key positions are needed. In this work we used the AEI SEM images obtained from traditional CD-SEM flow, processed with ASML’s MXP (Metrology for eXtreme Performance) tool, and used the extracted CD gauges and massive EP gauges to train a deeplearning Newron Etch model. In the approach, MXP reduced the AEI metrology random errors and shape fitting measurement error and provides better pattern coverage with massive reliable CD and EP gauges, Newron Etch captures complex and unknown physical and chemical effects learned from wafer data. Results shows that MXP successfully extracted stable contour from AEI SEM for various pattern types. Three etch models are calibrated and compared: CD based EEB model (Effective Etch Bias), CD+EP based EEB model, and CD+EP based Newron etch model. CD based EEB model captures the major trend of the etch process. Including EP gauges helps EEB model with about 10% RMS reduction on prediction. Integration of MXP (CD+EP) and Newron Etch model gains about 45% prediction RMS reduction compared to baseline model. The good prediction of Newron Etch is also verified from wafer SEM overlay on complex-shape patterns. This result validates the effectiveness of ASML’s solution of deep learning etch model integration with MXP AEI’s massive wafer data extraction from etch process, and will help to provide accurate and reliable etch modeling for advanced node etch OPC correction in semiconductor manufacturing.
