Mr. Yukio Takabayashi Profile

Yukio Takabayashi

Senior General Manager at Canon Inc

SPIE Involvement:

Author

Publications (24)

Proceedings Article | 12 November 2024 Presentation + Paper

Presentation + Paper

Nanoimprint lithography performance and applications

Yushi Yamakawa, Toshihiro Ifuku, Masami Yonekawa, Kazuhiro Sato, Tomohiro Saito, Toshiki Ito, Kiyohito Yamamoto, Mitsuru Hiura, Yukio Takabayashi, Keita Sakai

Proceedings Volume 13216, 132161I (2024) https://doi.org/10.1117/12.3034540

KEYWORDS: Nanoimprint lithography, Optical lithography, Optical components, Semiconductors, Semiconducting wafers, Printing, Particles, Overlay metrology, Optical design

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Proceedings Article | 26 August 2024 Paper

Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Shinichi Shudo, Hirotoshi Torii, Yoshio Suzaki, Atsushi Kimura, Kiyohito Yamamoto, Mitsuru Hiura, Keita Sakai, Yukio Takabayashi

Proceedings Volume 13177, 1317708 (2024) https://doi.org/10.1117/12.3034104

KEYWORDS: Overlay metrology, Optical lithography, Semiconducting wafers, Molybdenum, Manufacturing

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Proceedings Article | 9 April 2024 Presentation + Paper

Presentation + Paper

Nanoimprint lithography performance advances for new application spaces

Toshihiro Ifuku, Masami Yonekawa, Kazuki Nakagawa, Kazuhiro Sato, Tomohiro Saito, Sentaro Aihara, Toshiki Ito, Kiyohito Yamamoto, Mitsuru Hiura, Keita Sakai, Yukio Takabayashi

Proceedings Volume 12956, 1295603 (2024) https://doi.org/10.1117/12.3012070

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Overlay metrology, Optical lithography, Lithography, Molybdenum, Ecosystems, Printing, Metrology, Particles

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15 to 20% of the minimum half pitch. For 14nm, this means 2.1 to 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL, an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. To establish a new lithographic production solution requires the support of an ecosystem in order to enable seamless insertion of the technology. In this paper, review the current performance of Canon’s and then move on to discuss a variety of ecosystem technologies including drop pattern generation, NIL process simulation, virtual metrology support and pattern transfer techniques that can be applied to different markets. Finally, we touch on other applications that can be addressed with NIL and show some processing examples.

Proceedings Article | 21 November 2023 Presentation + Paper

Presentation + Paper

Establishing a nanoimprint lithography ecosystem

Hideo Tanaka, Naoki Maruyama, Mitsuru Hiura, Yoshio Suzaki, Atsushi Kimura, Kiyohito Yamamoto, Takahiro Matsumoto, Kenji Yamamoto, Yukio Takabayashi

Proceedings Volume 12751, 127510D (2023) https://doi.org/10.1117/12.2687092

KEYWORDS: Nanoimprint lithography, Semiconductors, Semiconductor manufacturing, Manufacturing, Optical lithography, Viscosity, Manufacturing equipment, Distortion, Actuators

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present the most recent results for cross matched machine overlay and single machine overlay. For defectivity, we review random defect generation and particle adders. We then move on to discuss the technologies being introduced to establish a robust ecosystem for NIL. Topics include pattern transfer, simulation and data analytics designed to shorten cycles of learning. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Proceedings Article | 29 September 2023 Paper

Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Hiromichi Hara, Naoki Maruyama, Mitsuru Hiura, Yoshio Suzaki, Atsushi Kimura, Kiyohito Yamamoto, Takahiro Matsumoto, Kenji Yamamoto, Yukio Takabayashi

Proceedings Volume 12915, 1291505 (2023) https://doi.org/10.1117/12.2684302

KEYWORDS: Nanoimprint lithography, Overlay metrology, Semiconducting wafers, Particles, Semiconductors, Distortion, Optical lithography, Optical components, Molybdenum, Printing

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For defectivity, we review random defect generation, particle adders and mask inspection methods. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Proceedings Article | 1 May 2023 Presentation + Paper

Presentation + Paper

Advances and applications in nanoimprint lithography

Naoki Maruyama, Kazuhiro Sato, Yoshio Suzaki, Satoru Jimbo, Isamu Yamashita, Kenji Yamamoto, Kiyohito Yamamoto, Mitsuru Hiura, Yukio Takabayashi

Proceedings Volume 12497, 124970D (2023) https://doi.org/10.1117/12.2658127

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Overlay metrology, Particles, Optical lithography, Logic, Distortion, Semiconductors, Optical components, Molybdenum

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay, edge placement error and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For edge placement error (EPE), we discuss progress made towards addressing EPE budgets for memory devices. For defectivity, we review random defect generation, particle adders and mask inspection methods. NIL usability cases are also examined. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Proceedings Article | 1 December 2022 Presentation + Paper

Presentation + Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Toshihiro Ifuku, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Byung Jin Choi, Teresa Estrada, Douglas Resnick

Proceedings Volume 12293, 122930E (2022) https://doi.org/10.1117/12.2643212

KEYWORDS: Nanoimprint lithography, Photomasks, Semiconducting wafers, Overlay metrology, Particles, Semiconductors, Optical lithography, Distortion, Logic

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For defectivity, we review random defect generation, particle adders and mask inspection methods. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Proceedings Article | 16 September 2022 Paper

Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Kenichi Kobayashi, Hirotoshi Torii, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Jin Choi, Teresa Estrada

Proceedings Volume 12325, 1232504 (2022) https://doi.org/10.1117/12.2640651

KEYWORDS: Photomasks, Semiconductors, Optical lithography, Manufacturing, Semiconducting wafers, Etching, Molybdenum, Logic, Helium

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

Proceedings Article | 25 May 2022 Presentation + Paper

Presentation + Paper

Nanoimprint lithography: today and tomorrow

Hirotoshi Torii, Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Yoshio Suzaki, Toshiki Ito, Kiyohito Yamamoto, Byung Jin Choi, Teresa Estrada

Proceedings Volume 12054, 1205403 (2022) https://doi.org/10.1117/12.2615740

KEYWORDS: Nanoimprint lithography, Photomasks, Etching, Optical lithography, Semiconducting wafers, Molybdenum, Logic, Helium, Semiconductors, Overlay metrology

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

Proceedings Article | 9 March 2021 Presentation + Paper

Presentation + Paper

Nanoimprint performance improvements for high volume semiconductor device manufacturing

Mitsuru Hiura, Yukio Takabayashi, Atsushi Kimura, Hiroshi Morohoshi, Yoshio Suzaki, Takahiro Matsumoto, Anshuman Cherala, Jin Choi

Proceedings Volume 11610, 1161005 (2021) https://doi.org/10.1117/12.2584675

KEYWORDS: Optical alignment, Semiconducting wafers, Nanoimprint lithography, Photomasks, Overlay metrology, Manufacturing, Semiconductors, Semiconductor manufacturing, Particles, Optical lithography

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL and attractive solution. The purpose of this paper is to review the performance improvements related to overlay, resolution and pattern transfer. Improvements in overlay include control methods such as imprint force, mask to wafer tip/tilt and pneumatic controls at the wafer edge. We also introduce the pattern transfer scheme used to etch features with half pitches below 20nm.

Proceedings Article | 21 September 2020 Presentation

Presentation

Computational lithography and its role in nanoimprint lithography for semiconductor device manufacturing

Toshiya Asano, Junichi Seki, Yuichiro Oguchi, Naoki Kiyohara, Koshiro Suzuki, Kohei Nagane, Hiromi Hiura, Keita Sakai, Mitsuru Hiura, Osamu Morimoto, Yukio Takabayashi, Takehiko Iwanaga

Proceedings Volume 11518, 115180V (2020) https://doi.org/10.1117/12.2574629

KEYWORDS: Nanoimprint lithography, Photomasks, Manufacturing, Optical lithography, Stochastic processes, Computational lithography, Semiconductor manufacturing, Semiconductors, Photoresist processing, Ultraviolet radiation

Read Abstract +

Proceedings Article | 23 March 2020 Paper

Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Atsushi Kimura, Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Keita Sakai, Hiroshi Morohoshi, Toshiya Asano, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 11324, 113240B (2020) https://doi.org/10.1117/12.2551985

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Optical alignment, Photomasks, Distortion, Overlay metrology, Optical lithography, Wafer testing, Lithography, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results. On test wafers, XMMO of 3.2nm and 2.8nm in x and y respectively was demonstrated. There is also an opportunity to further improve results by applying wafer chucks with better flatness specifications. Further advances have also been made through the application of a multi-wavelength alignment strategy. Finally, we discuss how computational methods can enhance NIL productivity and reduce the number of learning cycles

Proceedings Article | 26 September 2019 Presentation + Paper

Presentation + Paper

Patterning, mask life, throughput and overlay improvements for high volume semiconductor manufacturing using nanoimprint lithography

Osamu Morimoto, Takehiko Iwanaga, Yukio Takabayashi, Keita Sakai, Wei Zhang, Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Jin Choi

Proceedings Volume 11148, 111480M (2019) https://doi.org/10.1117/12.2535912

KEYWORDS: Photomasks, Optical lithography, Nanoimprint lithography, Stochastic processes, Semiconductor manufacturing, Particles, Semiconducting wafers, Lithography, Manufacturing equipment, Capillaries

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

Proceedings Article | 27 June 2019 Paper

Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Toshiya Asano, Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 11178, 111780I (2019) https://doi.org/10.1117/12.2532522

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 27 June 2019 Paper

Paper

Status of overlay performance for NIL high volume manufacturing

Tatsuya Hayashi, Yukio Takabayashi, Mitsuru Hiura, Takehiko Iwanaga, Hiroshi Morohoshi, Takamitsu Komaki

Proceedings Volume 11178, 111780J (2019) https://doi.org/10.1117/12.2536315

KEYWORDS: Semiconducting wafers, Distortion, Nanoimprint lithography, Overlay metrology, Photomasks, Wafer testing, Optical alignment, Source mask optimization, Lithography, Optical lithography

Read Abstract +

Nanoimprint lithography (NIL) techniques are known to possess replication resolution below 5nm. A specific form of imprint lithography using jetted resist has been developed for manufacturing advanced CMOS memory. Canon’s NIL process involves field-by-field inkjet deposition of a low viscosity resist fluid followed by imprinting with nano-scale precision overlay. A mask with a relief structure is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is separated from the substrate leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. The linear response of the HODC system was demonstrated for multiple high order terms and on test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was achieved. Additionally an SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications.

Proceedings Article | 26 March 2019 Presentation + Paper

Presentation + Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Hiroshi Morohoshi, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 10958, 109580B (2019) https://doi.org/10.1117/12.2514924

KEYWORDS: Semiconducting wafers, Optical alignment, Wafer testing, Nanoimprint lithography, Distortion, Overlay metrology, Photomasks, Source mask optimization, Optical lithography, Lithography

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Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. On test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was demonstrated. SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications. Comparable results were also achieved on device wafers by applying a multi-wavelength alignment strategy and a feed forward strategy to realize align signal convergence within the allocated 0.60 second budget.

Proceedings Article | 26 March 2019 Paper

Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Toshiya Asano, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 10958, 109580G (2019) https://doi.org/10.1117/12.2514925

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 13 July 2017 Paper

Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Masami Yonekawa, Takahiro Nakayama, Kazuki Nakagawa, Toshihiro Maeda, Yoichi Matsuoka, Keiji Emoto, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10454, 104540R (2017) https://doi.org/10.1117/12.2279365

KEYWORDS: Semiconducting wafers, Curtains, Polishing, Lithography, Liquids, Ceramics, Nanoimprint lithography, Particles, Control systems, Semiconductor manufacturing, Photomasks

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Proceedings Article | 21 March 2017 Presentation + Paper

Presentation + Paper

Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance

Yukio Takabayashi, Mitsuru Hiura, Hiroshi Morohoshi, Nobuhiro Kodachi, Tatsuya Hayashi, Atsushi Kimura, Takahiro Yoshida, Kazuhiko Mishima, Yoshio Suzaki, Jin Choi

Proceedings Volume 10144, 1014405 (2017) https://doi.org/10.1117/12.2258385

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Optical alignment, Distortion, Overlay metrology, Semiconductor manufacturing, Lithography, Semiconductors, Particles, Actuators, Source mask optimization

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Proceedings Article | 21 March 2017 Paper

Paper

Improved defectivity and particle control for nanoimprint lithography high-volume semiconductor manufacturing

Takahiro Nakayama, Masami Yonekawa, Yoichi Matsuoka, Hisanobu Azuma, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10144, 1014407 (2017) https://doi.org/10.1117/12.2257647

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Semiconducting wafers, Curtains, Ceramics, Surface finishing, Polishing

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Proceedings Article | 20 October 2016 Paper

Paper

Nanoimprint system development and status for high volume semiconductor manufacturing

Hiromi Hiura, Yukio Takabayashi, Tsuneo Takashima, Keiji Emoto, Jin Choi, Phil Schumaker

Proceedings Volume 10032, 100320E (2016) https://doi.org/10.1117/12.2248363

KEYWORDS: Nanoimprint lithography, Overlay metrology, Particles, Photomasks, Semiconducting wafers, Curtains, Lithography, Semiconductors, Actuators, Data modeling

Read Abstract +

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Proceedings Article | 4 October 2016 Paper

Paper

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

Yoichi Matsuoka, Junichi Seki, Takahiro Nakayama, Kazuki Nakagawa, Hisanobu Azuma, Kiyohito Yamamoto, Chiaki Sato, Fumio Sakai, Yukio Takabayashi, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 9985, 99851G (2016) https://doi.org/10.1117/12.2243114

KEYWORDS: Photomasks, Lithography, Nanoimprint lithography, Semiconducting wafers, Semiconductors, Particles, Semiconductor manufacturing, Curtains, Image resolution, Manufacturing

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Proceedings Article | 22 March 2016 Paper

Paper

Nanoimprint system development and status for high-volume semiconductor manufacturing

Tsuneo Takashima, Yukio Takabayashi, Naosuke Nishimura, Keiji Emoto, Takahiro Matsumoto, Tatsuya Hayashi, Atsushi Kimura, Jin Choi, Philip Schumaker

Proceedings Volume 9777, 977706 (2016) https://doi.org/10.1117/12.2219001

KEYWORDS: Photomasks, Nanoimprint lithography, Lithography, Overlay metrology, Semiconductor manufacturing, Semiconductors, Semiconducting wafers, Particles, Capillaries, Ultraviolet radiation, Distortion, High volume manufacturing, Actuators

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Proceedings Article | 22 March 2016 Paper

Paper

Defectivity and particle reduction for mask life extension, and imprint mask replication for high-volume semiconductor manufacturing

Keiji Emoto, Fumio Sakai, Chiaki Sato, Yukio Takabayashi, Hitoshi Nakano, Tsuneo Takabayashi, Kiyohito Yamamoto, Tadashi Hattori, Mitsuru Hiura, Toshiaki Ando, Yoshio Kawanobe, Hisanobu Azuma, Takehiko Iwanaga, Jin Choi, Ali Aghili, Chris Jones, J. W. Irving, Brian Fletcher, Zhengmao Ye

Proceedings Volume 9777, 97770C (2016) https://doi.org/10.1117/12.2219036

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Dry etching, Semiconducting wafers, Curtains, Liquids, Ceramics, Overlay metrology

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Showing 5 of 24 publications

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