The common process window of EUV patterning is being limited when the 1-dimensional (1D) pitch shrinks to 32nm or below. There are many investigations and studies that propose an alternative EUV photomask absorber to mitigate photomask 3-dimensional (3D) topology effects and can partially mitigate the contrast fading effect and reduce through pitch best focus shift.1,2,3 Another method to counter photomask 3D effects, is sub-resolution assistant features (SRAFs). SRAF insertion is one possible way to create a dense optical environment, which will prevent strong best focus shift from semi-isolated to isolated features. However, the side effect of SRAF insertion is unwanted SRAF printing occurring on the surface or bottom of the photoresist.4 In order to predict the partial removal or small residues of photoresist after the lithographic development process, a flow of compact photoresist 3D modeling (R3D) in conjunction with stochastic modeling can be adopted. In this paper, a bright field EUV photomask with regular 1D line-space grid design and positive tone development (PTD) are considered. The SEM images of through pitch 1D structures with various sizes of SRAFs are collected. To quantify SRAF printing, pixel brightness is compared to resist-opened background area, the printing SRAF regions can then be identified and clustered. Compact resist stochastic modeling is also performed by line-width roughness (LWR) sampling and used to predict SRAFs printing pixels by using Average Printing Area (APA) method with R3D modeling.5 Therefore, not only severe SRAF printing events can be predicted well, but also the accurate prediction of SRAF printing with very low probabilities can also be achieved.
The fast rigorous model (FRM) is a first principles solver based on sequential simulations of photochemical reactions in photoresists. We report the evaluation of FRM relative to compact models (CM1) for NTD OPC model accuracy. We demonstrate equivalent or better accuracy to CM1 when FRM is combined with a CM1 model of the same composition. In the case of CTR to FRM comparison, FRM is 34% more accurate in calibration and prediction on average across 20 testcases. FRM is 5% more predictive than the most complex CM1 modelform tested with similar calibration accuracy. FRM supplemented with limited CM1 terms provides better verification accuracy for SRAF printing and hotspot detection. Further, the input data needed to train the FRM model in order to achieve high predictive accuracy is a fraction (1-5%) of that needed by more complex CM1 modelforms. Finally, we show through the Akaike Information Criteria method that FRM is more predictive than an equivalent CM1 model based on the degrees of freedom in the modelform and quantity of data available.
KEYWORDS: Optical proximity correction, Electron beam lithography, 3D modeling, Inspection, Calibration, Lithography, Data modeling, Time metrology, Semiconducting wafers, Scanning electron microscopy
A method to perform Optical Proximity Correction (OPC) model calibration that is also sensitive to lithography failure modes and takes advantage of the large field of view (LFoV) e-beam inspection, is presented. To improve the coverage of the OPC model and the accuracy of the after development inspection (ADI) pattern hotspots prediction - such as trench pinching or bridging in complex 2D routing patterns - a new sampling plan with additional hotpot locations and the corresponding contours input data is introduced. The preliminary inspected hotspots can be added to the traditional OPC modeling flow in order to provide extra information for a hotspot aware OPC model. A compact optical/resist 3D modeling toolkit is applied to interpret the impact of photoresist (PR) profiles, as well as accurate predictions of hotspot patterns occurring at the top or bottom of the PR. A contour-based modeling flow is also introduced that uses a site or edge based calibration engine, to better describe hotspot locations in the hotspot aware OPC model calibration. To quantify the improvement in pattern coverage in the modeling flow, feature vectors (FVs) analysis and comparisons between the conventional and the hotspot aware OPC models is also presented.[1] The time and cost of using conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure such a large amount of CD gauges are prohibitive. By contrast, using LFoV e-beam inspection with improved training algorithm to extract fine contours from wafer hotspots, a hotspot aware OPC model can predict ADI hotspots with a higher capture rate as compared to main feature OPC model. Presumably, a hotspot-aware modeling flow based on LFoV images/contours not only benefits users by improving the capture rate of the lithography defects, but also brings the advantages to the failure mode analysis for the post-etch stage.
The method to perform Optical Proximity Correction (OPC) model calibration with contour-based input data from both small field of view (SFoV) and large field of view (LFoV) e-beam inspection is presented. For advanced OPC models - such as Neural Network Assisted Models (NNAM) [1], pattern sampling is a critical topic, where pattern feature vectors utilized in model training, such as image parameter space (IPS) is critical to ensure accurate model prediction [2-5]. In order to improve the design space coverage, thousands of gauges with unique feature vector combinations might be brought into OPC model calibration to improve pattern coverage. The time and cost in conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure this large amount of CD gauges is costly. Hence, an OPC modeling solution with contourbased input has been introduced [6]. Built on this methodology, a single inspection image and SEM contour can include a large amount of information along polygon edges in complex logic circuit layouts. Namely, a better feature vector coverage could be expected [7]. Furthermore, much less metrology time is needed to collect the OPC modeling data comparing to conventional CD measurements. It is also shown that by utilizing large field 2D contours, which are difficult to characterize by CD measurements, in model calibration the model prediction of 2D features is improved. Finally, the model error rms of conventional SFoV modeling and LFoV contour modeling between SEM contours and simulation results are compared.
As the technology node for the semiconductor manufacturing approaches advanced nodes, the scattering-bars (SBs) are more crucial than ever to ensure a good on-wafer printability of the line space pattern and hole pattern. The main pattern with small pitches requires a very narrow PV (process variation) band. A delicate SB addition scheme is thus needed to maintain a sufficient PW (process window) for the semi-iso- and iso-patterns. In general, the wider, longer, and closer to main feature SBs will be more effective in enhancing the printability; on the other hand, they are also more likely to be printed on the wafer; resulting in undesired defects transferable to subsequent processes. In this work, we have developed a model based approach for the scattering-bar printing avoidance (SPA). A specially designed optical model was tuned based on a broad range of test patterns which contain a variation of CDs and SB placements showing printing and non-printing scattering bars. A printing threshold is then obtained to check the extra-printings of SBs. The accuracy of this threshold is verified by pre-designed test patterns. The printing threshold associated with our novel SPA model allows us to set up a proper SB rule.
KEYWORDS: Metrology, Optical proximity correction, Calibration, Data modeling, Photomasks, Lithography, 3D modeling, Electrons, Scanning electron microscopy, Semiconducting wafers, Monte Carlo methods
Optical Proximity Correction (OPC) has continually improved in accuracy over the years by adding more physically based models. Here, we further extend OPC modeling by adding the Analytical Linescan Model (ALM) to account for systematic biases in CD-SEM metrology. The ALM was added to a conventional OPC model calibration flow and the accuracy of the calibrated model with the ALM was compared to the standard model without the ALM using validation data. Without using any adjustable parameters in the ALM, OPC validation accuracy was improved by 5%. While very preliminary, these results give hope that modeling metrology could be an important next step in OPC model improvement.
Resist profile shapes become important for 22nm node and beyond as the process window shrinks. Degraded profile shapes for example may induce etching failures. Rigorous resist simulators can simulate a 3D resist profile accurately but they are not fast enough for correction or verification on a full chip. Compact resist models are fast but have traditionally modeled the resist in two dimensions. They provide no information on the resist loss and sidewall angle. However, they can be extended to predict resist profiles by proper setting of optical parameters and by accounting for vertical effects. Large resist shrinkages in NTD resists can also be included in the compact model. This article shows how a compact resist model in Calibre can be used to predict resist profiles and resist contours at arbitrary heights.
With the introduction of negative tone develop (NTD) resists to production lithography nodes, multiple NTD resist modeling challenges have surpassed the accuracy limits of the existing modeling infrastructure developed for the positive polarity process. We report the evaluation of two NTD resist modeling algorithms. The new modeling terms represent, from the first principles, the NTD resist mechanisms of horizontal shrink and horizontal development bias. Horizontal shrink describes the impact of the physical process of out-gassing on remaining resist edge location. Horizontal development bias accounts for the differential in the peak and minimum development rate with exposure intensity observed in NTD formulations. We review specific patterning characteristics by feature type, modeling accuracy impact presented by these NTD mechanisms, and their description in our compact models (Compact Model 1, CM1). All the new terms complement the accuracy advantage observed with existing CM1 resist modeling infrastructure. The new terms were tested on various NTD layers. The results demonstrate consistent model accuracy improvement for both calibration and verification. Furthermore, typical NTD model fitting challenges, such as large SRAF-induced wafer CD jump, can be overcome by the new NTD terms. Finally, we propose a joint-tuning approach for the calibration of compact models for the NTD resist.
As critical dimensions decrease for 32-nm node and beyond, the resist loss increases and resist patterns become more vulnerable to etching failures. Traditional optical proximity correction (OPC) models only consider two-dimensional (XY) contours and neglect height (Z) variations. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip. However, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. We show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration. The model can then be used to identify toploss hotspots on a full chip and, in some cases, for correction of these patterns. In addition, the article will show how the model can be made more accurate by accounting for some 3-D effects like diffusion through height.
As Critical Dimension (CD) sizes decrease for 32 nm node and beyond, resist loss increases and resist patterns
become more vulnerable to etching failures. Traditional OPC models only consider 2D contours and neglect height
variations. Rigorous resist simulators can simulate a 3D resist profile but they are not fast enough for correction or
verification on a full chip. However, resist loss for positive tone resists is mainly driven by optical intensity
variations which are accurately modeled by the optical portion of an OPC model. In this article, we show that a
CalibreTM CM1 resist model can be used to determine resist loss by properly selecting the optical image plane for
calibration. The model can then be used to identify toploss hotspots on a full chip and in some cases to correction of
these patterns. In addition, the article will show how the model can be made more accurate by accounting for some
3D effects like diffusion through height.
For 20 nm technology, rigorous electromagnetic field (EMF) simulation is important to predict correct lithography performance in mask development. Three mask absorbers with different total thickness and materials are used in the paper to explore the impact of thickness. The side wall profiles could also have the potential to change the process variation band (PV Band). By using rigorous EMF simulation to calculate a usual process variation band, the result shows the best focus shift changes through patterns, and leads to a CD impact caused by defocus. A new PV Band setting with side wall angle as a variable is used to show the significant impact.
Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary
before mass production. One effective way to mitigate the defect impact is to increase the distance between the
defects and feature boundaries such that the defects will not affect the printing of the features. Some algorithms
have been developed to move the whole layout within the exposure field in order to avoid all defect impact.
However, in reality the die size is usually much smaller than the exposure field, such that one blank is packed
with multiple copies of the die, and each die can be placed independently within the exposure field. In this
paper, we develop an EUV reticle placement algorithm to maximize the number of valid dies that are immune
to defects. Given the layout of a die and a defective blank, we first apply a layout relocation algorithm to find
all feasible regions for the die on the blank. Then we develop an efficient placement algorithm to place the dies
within the feasible regions one at a time until all feasible regions are fully occupied. The simulation results show
that our algorithm is able to find a solution efficiently and the number of valid dies placed by our algorithm is
very close to the optimal solution.
In the very low k1 regime in optical lithography, aggressive RET such as strong off-axis illumination causes significant
forbidden pitches and lithography hotspots for aggressive designs. Various lithography retargeting techniques have been
introduced to mitigate these process window failures. This paper proposes to bring the lithography target optimization
into the Source-Mask Optimization (SMO) flow to achieve better SMO solutions at an earlier process development
stage. Through this tight integration of lithography target optimization and source mask optimization, lithography target,
source, and mask can be tuned together to provide the best overall process window for the newly defined targets. This
improvement is demonstrated using a simple SMO test case for the 20-nm metal layer. Then at the later development
stage, retargeting rules can be extracted from these optimized lithography targets, and they can be applied in the normal
mask optimization process. This lithography target optimization flow can provide a faster tuning process for the
lithography target rules at an early process development stage, and can provide optimized retarget rules for mask
optimization process too. New challenges for retargeting in double patterning lithography are also discussed.
For the logic generations of the 15 nm node and beyond, the printing of pitches at 64nm and below are needed.
For EUV lithography to replace ArF-based multi-exposure techniques, it is required to print these patterns in
a single exposure process. The k1 factor is roughly 0.6 for 64nm pitch at an NA of 0.25, and k1 ≈ 0.52 for
56nm pitch. These k1 numbers are of the same order at which model based OPC was introduced in KrF and
ArF lithography a decade or so earlier. While we have done earlier work that used model-based OPC for the
22nm node test devices using EUV,1 we used a simple threshold model without further resist model calibration.
For 64 nm pitch at an NA of 0.25, the OPC becomes more important, and at 56nm pitch it becomes critical.
For 15 nm node lithography, we resort to a full resist model calibration using tools that were adapted from
conventional optical lithography. We use a straight shrink 22 nm test layout to assess post-OPC printability of
a metal layer at pitches at 64 nm and 56 nm, and we use this information to correct test layouts.
Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other
alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over
traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This
paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface
between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned
Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn
design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design
rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design
rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow.
Only joint optimization in design rules between design, decomposition and process constraints can achieve the best
scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware
design tools are needed so that final designs can meet all DPT restricted design rules.
Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before
EUV or any other advanced patterning techniques become available. In general, there are two major double patterning
techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double
Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process
capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their
applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough
discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadence's Encounter
Digital Implementation System (EDI System).
KEYWORDS: Photomasks, Optical lithography, Etching, Dielectrics, Double patterning technology, Image processing, Logic, Scanning electron microscopy, Back end of line, Metals
Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to
its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques
was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were
mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic
field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed
into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied
Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design
capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big
advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity
control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.
Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less
studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the
design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend
on contact area and shape, larger CER results in significant change in a device current. In this paper, we first
propose a CER model based on power spectral density function which is a function of RMS edge roughness,
correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology
for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first
dissect the contact with a same distance, and then calculate the effective resistance considering both the shape
weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.
We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm
technology node by integrating it into standard semiconductor process flows because we believe that device integration
exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In
this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and
first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art
defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably
higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV
lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the
0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.
Accurate and flexible simulation methods may be used to further a researcher's understanding
of how complex resist effects influence the patterning of critical structures. In this work, we
attempt to gain insight into the behavior of a state-of-the-art EUV resist through the use of
stochastic resist simulation. The statistics of photon and molecule counting are discussed. A
discrete, probabilistic ionization and electron scattering simulator for acid generation at EUV is
discussed. At EUV, acid generators are hypothesized to be activated by secondary electrons
yielded by ionization of the resist upon absorption of photons. Model fit to experimental data of
mean CD and LWR for a state-of-the-art EUV resist is shown.
In the low k1 regime, optical lithography can be extended further to its limits by advanced computational lithography
technologies such as Source-Mask Optimization (SMO) without applying costly double patterning techniques. By cooptimizing
the source and mask together and utilizing new capabilities of the advanced source and mask manufacturing,
SMO promises to deliver the desired scaling with reasonable lithography performance. This paper analyzes the
important considerations when applying the SMO approach to global source optimization in random logic applications.
SMO needs to use realistic and practical cost functions and model the lithography process with accurate process data.
Through the concept of source point impact factor (SPIF), this study shows how optimization outputs depend on SMO
inputs, such as limiting patterns in the optimization. This paper also discusses the modeling requirements of lithography
processes in SMO, and it shows how resist blur affect optimization solutions. Using a logic test case as example, the
optimized pixelated source is compared with the non-optimized source and other optimized parametric sources in the
verification. These results demonstrate the importance of these considerations during optimization in achieving the best
possible SMO results which can be applied successfully to the targeted lithography process.
In advanced photolithography process for manufacturing integrated circuits, the critical pattern sizes that need to be
printed on wafer are much smaller than the wavelength. Thus, source optimization (SO) techniques play a critical role in
enabling a successful technology node. However, finding an appropriate illumination configuration involves intensive
computation simulations. EDA vendors have been developing the pixelated source optimization tools that co-optimize
both source and mask for a set of patterns. As an alternative approach, we have introduced design of experiments (DOE)
methodology for parameterized source optimization to minimize computation efforts while achieving comparable CDU
control for given design patterns.
In this paper, we present a Response Surface Methodology (RSM) that simplifies the response function and achieves the
optimization goal on multiple responses. Results have shown that the optimal input settings identified by this approach
are comparable with the pixelated source optimization results.
As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers
have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm
technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity
and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard
Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask
and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits
for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of
this study will demonstrate the lithographic performance contribution that can be obtained from these mask
optimization techniques in addition to what source optimization can achieve.
Accurate and flexible simulation methods may be used to further a researcher's
understanding of how complex resist effects influence the patterning of critical structures. In
this work, we attempt to gain insight into the behavior of a state-of-the-art EUV resist through
the use of stochastic resist modeling. The statistics of photon and molecule counting are
discussed. The acid generation mechanism at EUV is discussed. At lambda = 13.5 nm, the acid
generation mechanism may be similar to that found in electron beam resists: acid generators are
hypothesized to be activated by secondary electrons yielded by ionization of the resist matrix by
high-energy EUV photons, suggesting that acid generators may be activated some distance from
the absorption site. A discrete, probabilistic ionization and electron scattering model for PAG
conversion at EUV is discussed. The simulated effect of resist absorbance at EUV upon doseto-
size and line-width roughness is shown. The model's parameterized fit to experimental data
from a resist irradiated EUV are shown. Predictions of statistical resist responses such as CD
distribution and line-width roughness are compared with experimental data.
We describe progress in implementation of blur-based resolution metrics for EUV photoresists. Three sets of blur
metrics were evaluated as exposure-tool independent comparison methods using the Sematech-LBNL EUV microexposure
tool (MET) and ASML α-Demo Tool (ADT) full-field EUV scanner. For the two EUV resists studied here,
deprotection blurs of 15 nm are consistently measured using blur estimation methods based on corner rounding, contact
hole exposure latitude, and process window fitting using chemical amplification lumped parameter models. Agreement
between methods and exposure tools appears excellent. For both resists, SRAM-type lithographic diagnostic patterns at
80 nm pitch are only modestly sensitive to OPC blur compensation and display robust printability (RELS ~ ILS near 50
μm-1 for multiple trench geometries) on the ASML ADT. These findings confirm the continuing utility of blur-based
metrics in a) guiding resist selection for use in EUV process development and integration at the 22 nm logic node and
below, and b) providing an exposure-tool independent set of metrics for assessing progress in EUV resist development.
The EUV exposure tool settings and OPC strategies to be used for the 16 nm logic node are discussed. Imaging
simulation was done for various types of CD through pitch patterns to investigate the tradeoff between NA, illumination
settings, and resist diffusion blur. EUV optics still provides very good optical resolution at 56 nm min pitch, but resist
diffusion degrades imaging contrast significantly. The CD variations due to resist blur are relatively larger for EUV
lithography than they are for 193 nm lithography, because of the high quality of the EUV lithography images. EUV
shadowing effect and flare effect contribute additional CD variations, which need to be corrected and controlled.
Nonetheless, a resist blur of about 15 nm FWHM or better provides adequate imaging performance even with current
EUV optical settings of 0.25 NA and conventional illumination for 28 nm half-pitch applications. Experimental results
show that state-of-art EUV resists have resist blur values close to this requirement, although their current performance is
limited by resist material properties and processing conditions.
On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and
below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.
In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography;
the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV
mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of
mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV
lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The
CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured
overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided
ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first
interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.
The patterned integration wafers have been processed through metal deposition and polish at the contact level and are
now being patterned at the first interconnect level.
The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such
as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be
less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical
Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work
presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or
illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be
limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can
produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this
comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole
lithography and double patterning, comparing dimensional control through process window for each OPC
method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably
manufactured will also be explored.
KEYWORDS: Data modeling, 3D modeling, Scatterometry, Calibration, Optical proximity correction, 3D metrology, Critical dimension metrology, Lithography, Line edge roughness, Cadmium
The ability to manage critical dimensions (CDs) of structures on IC devices is vital to improving product yield
and performance. It is challenging to achieve accurate metrology data as the geometries shrink beyond 40 nm features.
At this technology node CDSEM noise and resist LER are of significant concerns1.
This paper examines the extendibility of scatterometry techniques to characterize structures that are close to limits of
lithographic printing and to extract full profile information for 2D and 3D features for OPC model calibration2. The resist
LER concerns are diminished because of the automatic averaging that scatterometry provides over the measurement pad;
this represents a significant added value for proper OPC model calibration and verification. This work develops a
comparison matrix to determine the impact of scatterometry data on OPC model calibration with conventional CDSEM
measurements. The paper will report test results for the OPC model through process data for accuracy and predictability.
Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
lithography-design optimization.
We have used ASML's full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an
Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks.
The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV
reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at
naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also
integrated into a standard process flow where the other layers were patterned using more conventional 193-nm
lithography techniques.
This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the
28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect
populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both
conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find
good correlations between reticle level defects and the resulting wafer exposure defects.
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
We report on a method to produce any type of phase-shift masks for EUV lithography. We have successfully fabricated an unattenuated phase-shift mask consisting of phase patterns and confirmed the expected performance of such a mask through resist printing at λ=13.3 nm. Finally actinic metrology reveals that these etched-multilayer masks, left without a capping layer, tend to degrade over time.
In this paper we present a method to characterize scattered light in lithography scanners based on the measurement of the modulation transfer function (MTF) of the lens. This method provides a description of scattered light at all length scales, or spatial frequencies, relevant to lithographic printing. We also introduce a new automated technique based on scatterometry that improves the precision and repeatability of the MTF measurement. Modeling of flare is important to quantify the impact of scattered light on the critical dimension of the features printed on chips. We have developed simulation methods based on actual data from our lithography scanners. Our model uses the MTF of the lens and the Fourier transform of the chip density map to calculate the flare distribution across the chips. We show that this approach is useful to understand how the characteristics of different scanners in our fabrication facilities might affect the critical dimension (CD) uniformity across our product chips.
The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them.
In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters.
We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.
Photoresist patterning experiments on the EUVL Engineering Test Stand using two masks with different types of architecture indicate that etched-multilayer binary masks can provide larger process latitude than standard patterned absorber masks. The trends observed in the experimental data are confirmed by rigorous electromagnetic simulations taking into account the mask structure, the imaging optics characteristics and the illumination conditions.
Rigorous electromagnetic scattering simulation is used to characterize mask diffraction for fine structures of various types of EUVL masks. The Cr/SiO2 absorber mask, the etched multilayer mask and the new refilled multilayer mask are studied for lithography performance for line and space features for 32 nm node. The combined process window of 25 nm ISO line, 50 nm METAL1 line and 30 nm POLY line in a 90 nm pitch, are compared at s of 0.6. The biased Cr/SiO2 absorber masks have 182 nm DOF, while the biased etched binary mask has a higher DOF of 190 nm and the biased etched refilled binary mask has a DOF of 192 nm. The biased Cr/SiO2 absorber masks show twice of CD variation and process window degradation due to variations in sidewall profiles than the etched and refilled multilayer binary masks. The void defect in the reflection region of multilayer structures can be repaired via deposition of transparent materials instead of absorbing materials when patterning the refilled multilayer masks. Simulations show that target CD and process window can be fully restored when the depth and width of repairing materials deposited for repair is optimized.
The impact of wafer and reticle anti-reflection coatings (ARCs) on the aerial image of ArF lithography scanners is measured using contrast curves and critical dimension (CD) analysis. The importance of a good ARC layer on the wafer appears to be greater than that of the reticle-ARC. In fact, for state-of-the-art lithography scanners, the influence of the reticle-ARC is practically undetectable. Numerical simulations are used to understand the relative contributions of the lens, the wafer and the reticle to the overall loss of contrast associated with non-optimized ARCs.
Rigorous electromagnetic scattering simulation is used to characterize mask diffraction of various EUVL mask structures. Planar multilayer masks with three kinds of absorber stacks and new subtractive (binary, att-PSM, alt-PSM) etched multilayer masks are studied for lithography performance for line and space features in the 45 nm node. The simulation results for process window show that the combined depth of focus of the Cr/SiO2 absorber stack masks is about 320 nm maximum with sigma of 0.8 when mask CD biases are applied. The biased etched binary mask has a higher DOF of 360 nm at sigma = 0.6. The line width variations caused by the absorber thickness changes are shown to be about 2 nm due the interference effects and image placement errors (IPE) are 4-7 nm with a 0.4 nm variation. The consideration of a full 2% EUV illumination bandwidth decreases the interference effects by 50%. The etched binary mask is not affected by such phenomenon and provides better contrast. The H-V bias and IPE results of absorber stacks show a linear dependence of absorber thickness. The etched binary multilayer mask has less H-V bias and IPE due to its smaller effective thickness. A simple alternating PSM structure created by the subtractive multilayer mask patterning technique is also proposed and it shows a larger 722 nm DOF.
The imaging performance of non-planar topographies in EUV masks for both partially repaired defects and non-planar attenuating phase-shifting masks made with repair treatments are evaluated using rigorous electromagnetic simulation with TEMPEST. Typical topographies produced by treatment techniques in the literature such as removal of top layers and compaction produced by electron-beam heating are considered. Isolated defects on/near the surface repaired by material removal are shown to result in an image intensity within 5% of the clear field value. Deeply buried defects within the multilayer treated by electron-beam heating can be repaired to 3% of the clear field but over repair can result in some degradation. Compaction from a 6.938 nm period to a 6.312 nm period shows a 540° phase-shift and an intensity reduced to about 6% suggesting such a treatment may be used to create attenuated phase-shifting masks for EUV. The quality of the aerial image for such a mask is studied as a function of the lateral transition distance between treated and untreated regions.
Rigorous electromagnetic simulation with TEMPEST is used to examine the exposure and alignment processes for nano-imprint lithography with attenuating thin-film molds. Parameters in the design of topographical features of the nano-imprint system and material choices of the components are analyzed. The small feature size limits light transmission through the feature. While little can be done with auxiliary structures to attract light into small holes, the use of an absorbing material with a low real part of the refractive index such as silver helps mitigates the problem. Results on complementary alignment marks shows that the small transmission through the metal layer and the vertical separation of two alignment marks create the leakage equivalent to 1 nm misalignment but satisfactory alignment can be obtained by measuring alignment signals over a +/- 30 nm range.
Rigorous electromagnetic simulation with TEMPEST is used to examine the use of phase-shifting masks in EUV lithography. The effects of oblique incident illumination and mask patterning by ion-mixing of multilayers are analyzed. Oblique incident illumination causes streamers at absorber edges and causes position shifting in aerial images. The diffraction waves between ion-mixed and pristine multilayers are observed. The phase-shifting caused by stepped substrates is simulated and images show that it succeeds in creation of phase-shifting effects. The diffraction process at the phase boundary is also analyzed. As an example of EUV phase-shifting masks, a coma pattern and probe based aberration monitor is simulated and aerial images are formed under different levels of coma aberration. The probe signal rises quickly as coma increases as designed.
The Lithography Analysis using Virtual Access (LAVA) web site at http://cuervo.eecs.berkeley.edu/Volcano/ has been enhanced with new optical and deposition applets, graphical infrastructure and linkage to parallel execution on networks of workstations. More than ten new graphical user interface applets have been designed to support education, illustrate novel concepts from research, and explore usage of parallel machines. These applets have been improved through feedback and classroom use. Over the last year LAVA provided industry and other academic communities 1,300 session and 700 rigorous simulations per month among the SPLAT, SAMPLE2D, SAMPLE3D, TEMPEST, STORM, and BEBS simulators.
Rigorous electromagnetic simulation with TEMPEST is used to provide benchmark data and understanding of key parameters in the design of topographical features of alignment marks. Periodic large silicon trenches are analyzed as a function of wavelength (530-800 nm), duty cycle, depth, slope and angle of incidence. The signals are well behaved except when the trench width becomes about 1 micrometers or smaller. Segmentation of the trenches to form 3D marks shows that a segmentation period of 2-5 wavelengths makes the diffraction in the (1,1) direction about 1/3 to 1/2 of that in the main first order (1,0). Transmission alignment marks nanoimprint lithography using the difference between the +1 and -1 reflected orders showed a sensitivity of the difference signal to misalignment of 0.7%/nm for rigorous simulation and 0.5%/nm for simple ray-tracing. The sensitivity to a slanted substrate indentation was 10 nm off-set per degree of tilt from horizontal.
Mask quality issues in pushing lithography to features below 0.5(lambda) /NA are identified and quantified through simulation of mask interactions and images. Guidelines summarize the results from detailed studies of aberrations, phase-shift mask image imbalance, 3D phase defects and EUV buried defects. Programmed-probe based aberration targets are extended to distinguish both even and odd lens aberrations and their mask tolerance requirements are assessed. Complex diffraction coefficients and results for cross-talk simulation are used to set guidelines for phase-shifting mask design. An antireflection coating (50 nm MoO3) is shown to reduce cross-talk between trenches. Type, location and size data are given for 3D phase-defects and the end regions of lines are shown to be more vulnerable to CD variation. Results for buried 3D Gaussian defects in EUV multilayers show a worst isolated defect size of half of the resolution and that 2nm high defects of any size can be tolerated.
KEYWORDS: 3D modeling, Scattering, Extreme ultraviolet, Light scattering, Semiconducting wafers, Data modeling, Point spread functions, Photomasks, Radio propagation, Near field
Models for the printability of buried 3D EUV defect are analyzed and extended using rigorous electromagnetic simulation by TEMEPST. Parallel simulation on a network of workstation was used to examine the classical assumptions of coherent illumination, uniformly filling the entrance pupil and vertical propagation in the theoretical model of Gullikson for Gaussian defects. Results show that the limitation of the model is the lack of uniformity of filling the pupil for defects with diameter (2*sigma) larger than 0.20 (lambda) /NA at the wafer plane. Beyond this diameter the dip in the clear field intensity no longer follows the quadratic decrease with size and height of the model. Rather the dip quickly goes through its worst-case minimum intensity near 70 nm and then rises as the size further lowers the local surface slope. The worst-case image decrease from the clear field value for any sized Gaussian defect is roughly 18% per nm of height. Thus isolated Gaussian defects with height less than 2 nm will never reduce the field intensity to less than 60% of the clear field value.
A new interface has been created to link existing deposition/etching and electromagnetic simulation software, allowing the user to program deposition and etching conditions and then find the reflective properties of the resultant structure. The application studied in this paper is the problem of three-dimensional defects which become buried during fabrication of multilayer mirrors for extreme ultraviolet lithography. The software link reads in surface information in the form of linked triangles, determines all nodes within the triangles, and then creates nodes lying between triangles of different layers to create a 3- dimensional inhomogeneous matrix containing the materials' indices of refraction. This allows etching and depositions to be input into SAMPLE-3D, a multi-surface topology to be generated, and then the electromagnetic properties of the structure to be assessed with TEMPEST. This capability was used to study substrate defects in multilayer mirrors by programming a defect and then sputter-depositing some forty layers on top of the defect. Specifically examined was how the topography depended on sputter conditions and determined the defects' impact on the mirrors' imaging properties. While this research was focused on application to EUV lithography, the general technique may be extended to other optical processes such as alignment and mask defects.
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