Proc. SPIE. 5752, Metrology, Inspection, and Process Control for Microlithography XIX
KEYWORDS: Lithography, Data modeling, Calibration, Scanning electron microscopy, Scatterometry, Time metrology, Optical proximity correction, Semiconducting wafers, Scatter measurement, Process modeling
Evaluation and qualification of lithographic exposure tools is a crucial step in establishing high volume manufacturing processes for IC manufacturers. The data sampling offered by scatterometry can be as dense as that from ECD (electrical CD) for the qualification of the tool. In this paper, the CDs obtained from scatterometry measurements are compared with those obtained by ECD (electrical CD) measurements to show the cross-slit and cross-scan tool characteristics. Since scatterometry is still an order of magnitude slower than ECD, data from various sampling plans will be compared. Another important consideration of this study is to use scatterometry to generate OPC (optical proximity correction) models for the 45nm and 32nm nodes. An accurate measurement of the process to fit the model becomes very crucial in the very deep sub-micron regime. Currently, SEM measurements are performed but they are slow and their precision is not adequate. In this paper, scatterometry measured data will also be compared with SEM data for OPC model fit.
This paper compares two metrology methodologies, ECD (Electrical CD) and SCD (Spectroscopic CD), for the 45nm-node-like gate level. Measurements were taken on both metrology tools, for different features, and the data was processed to reflect the exposure tool’s fingerprint within the exposure field. ACLV (cross chip line-width variation) and through-focus measurements were also collected. There is a DC bias between the ECD and SCD. The cross slit and cross scan average plots are very similar between the two methods. The correlation between ECD and SCD gave R2 of 0.95 and 0.92 for 220nm and 480nm pitches respectively. Results showed that SCD is a viable candidate to replace ECD for characterizing the exposure system for the 45nm node. Data also showed that there are fundamental differences between the two methods that cannot be attributed to random errors. These differences account for less than 1nm at 3 σ.
With optical lithography prevailing into the year 2000, super-resolution processes pose a multitude of new challenges to the lithographer. Isolated to nested feature bias calls for 'pre- distorting' the photomask to compensate for proximity effects and print and etch biases in the mask and wafer manufacturing process. OPC (optical proximity correction) techniques have become a reality for sub-halfmicron lithography, and have initiated many discussions looking at the manufacturability of OPC masks. Regaining the lost DOF (depth of focus) due to ever shorter printing wavelength, and increasing yields by expanding process latitude have many IC manufacturers looking into PSMs (phase shift masks) as a viable but expensive enhancement technique for several [2-6] layers of the total [18-26] device mask set. This paper addresses manufacturability issues of various combinations of 'enhancement' masks.