Mr. Bharani Chava Profile

Bharani Chava

at Qualcomm Inc

SPIE Involvement:

Author

Publications (9)

Proceedings Article | 20 March 2019 Presentation + Paper

Backside power delivery as a scaling knob for future systems

Bharani Chava, Khaja Ahmad Shaik, Anne Jourdain, Sofiane Guissi, Pieter Weckx, Julien Ryckaert, Geert Van Der Plaas, Alessio Spessot, Eric Beyne, Anda Mocuta

Proceedings Volume 10962, 1096205 (2019) https://doi.org/10.1117/12.2514942

KEYWORDS: Metals, Logic, Standards development, Semiconducting wafers, Resistance, Clocks, Switches, Silicon, Chemical mechanical planarization, Device simulation

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Proceedings Article | 20 March 2018 Presentation + Paper

DTCO exploration for efficient standard cell power rails

Bharani Chava, Julien Ryckaert, Luca Mattii, Syed Muhammad Yasser Sherazi, Peter Debacker, Alessio Spessot, Diederik Verkest

Proceedings Volume 10588, 105880B (2018) https://doi.org/10.1117/12.2293500

KEYWORDS: Resistance, Ruthenium, Standards development, Metals, Optical lithography, Transistors, Copper, Capacitance, Resistors

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SPIE Journal Paper | 18 January 2018

Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules

Luca Mattii, Dragomir Milojevic, Peter Debacker, Mladen Berekovic, Syed Muhammad Yasser Sherazi, Bharani Chava, Marie Garcia Bardon, Pieter Schuddinck, Dimitrios Rodopoulos, Rogier Baert, Vassilios Gerousis, Julien Ryckaert, Praveen Raghavan

JM3, Vol. 17, Issue 01, 013503, (January 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.1.013503

KEYWORDS: Metals, Standards development, Electronic design automation, Optical lithography, Back end of line, Switching, CMOS technology, Lithography, Front end of line, Integrated circuit design

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Proceedings Article | 4 April 2017 Paper

Low track height standard cell design in iN7 using scaling boosters

S. M. Sherazi, C. Jha, D. Rodopoulos, P. Debacker, B. Chava, L. Matti, M. Bardon, P. Schuddinck, P. Raghavan, V. Gerousis, A. Spessot, D. Verkest, A. Mocuta, R. Kim, J. Ryckaert

Proceedings Volume 10148, 101480Y (2017) https://doi.org/10.1117/12.2257658

KEYWORDS: Front end of line, Metals, Back end of line, Standards development, CMOS technology, Capacitance, Logic, Semiconductors, Transistors

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SPIE Journal Paper | 25 February 2016

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Syed Muhammad Yasser Sherazi, Bharani Chava, Peter Debacker, Marie Garcia Bardon, Pieter Schuddinck, Farshad Firouzi, Praveen Raghavan, Abdelkarim Mercha, Diederik Verkest, Julien Ryckaert

JM3, Vol. 15, Issue 01, 013507, (February 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.1.013507

KEYWORDS: Optical lithography, Metals, Copper, Resistance, Extreme ultraviolet, Tungsten, Back end of line, Critical dimension metrology, Capacitance, CMOS technology

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Proceedings Article | 18 March 2015 Paper

Impact of a SADP flow on the design and process for N10/N7 metal layers

W. Gillijns, S. M. Y. Sherazi, D. Trivkovic, B. Chava, B. Vandewalle, V. Gerousis, P. Raghavan, J. Ryckaert, K. Mercha, D. Verkest, G. McIntyre, K. Ronse

Proceedings Volume 9427, 942709 (2015) https://doi.org/10.1117/12.2085923

KEYWORDS: Metals, Photomasks, Semiconducting wafers, Lithography, Optical lithography, Standards development, Capacitance, Optical proximity correction, Scanning electron microscopy, Manufacturing

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Proceedings Article | 18 March 2015 Paper

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Julien Ryckaert, Praveen Raghavan, Pieter Schuddinck, Huynh Bao Trong, Arindam Mallik, Sushil Sakhare, Bharani Chava, Yasser Sherazi, Philippe Leray, Abdelkarim Mercha, Jürgen Bömmels, Gregory McIntyre, Kurt Ronse, Aaron Thean, Zsolt Tökei, An Steegen, Diederik Verkest

Proceedings Volume 9427, 94270C (2015) https://doi.org/10.1117/12.2178997

KEYWORDS: Optical lithography, Metals, Transistors, Standards development, Logic, Resistance, Lithography, Extreme ultraviolet, Extreme ultraviolet lithography, Field effect transistors

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Proceedings Article | 18 March 2015 Paper

Standard cell design in N7: EUV vs. immersion

Bharani Chava, David Rio, Yasser Sherazi, Darko Trivkovic, Werner Gillijns, Peter Debacker, Praveen Raghavan, Ahmad Elsaid, Mircea Dusa, Abdelkarim Mercha, Julien Ryckaert, Diederik Verkest

Proceedings Volume 9427, 94270E (2015) https://doi.org/10.1117/12.2085739

KEYWORDS: Extreme ultraviolet, Photovoltaics, Deep ultraviolet, Standards development, Extreme ultraviolet lithography, Lithography, Photomasks, Source mask optimization, Scanners, Optical lithography

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Proceedings Article | 28 March 2014 Paper

Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM

Boris Vandewalle, Bharani Chava, Sushil Sakhare, Julien Ryckaert, Mircea Dusa

Proceedings Volume 9053, 90530Q (2014) https://doi.org/10.1117/12.2048079

KEYWORDS: Metals, Extreme ultraviolet lithography, Optical lithography, Etching, Extreme ultraviolet, Argon, Logic, Lithography, Computational lithography, Double patterning technology

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Showing 5 of 9 publications

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