Proceedings Article | 20 April 2011
Proc. SPIE. 7971, Metrology, Inspection, and Process Control for Microlithography XXV
KEYWORDS: Reticles, Metrology, Image processing, Scanners, Error analysis, Control systems, Photomasks, Optical alignment, Semiconducting wafers, Overlay metrology
To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally.
Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for
multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many
improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this
difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be
divided into 5 categories: scanner, process, reticle, metrology, and APC.
In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to
provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized
field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field
selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as
well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay
inside each field, rather than just at field corners.
Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their
limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay
performance. The ability to control correctable overlay components is paramount to achieving desired performance. In
addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we
show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment
metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve
the necessary overlay roadmap capability for current development efforts.
