Proceedings Article | 21 August 2013
KEYWORDS: Image compression, Digital signal processing, Computer programming, Video, Video coding, Video compression, Field programmable gate arrays, Image storage, Image processing, Model-based design
Engineering and products need to achieve real-time video encoding by DSP, but the
high computational complexity and huge amount of data requires that system has high data
throughput. In this paper, a real-time MPEG-4 video encoder is designed based on
TMS320C6416 platform. The kernel is the DSP of TMS320C6416T and FPGA chip f as the
organization and management of video data. In order to control the flow of input and output data.
Encoded stream is output using the synchronous serial port. The system has the clock frequency
of 1GHz and has up to 8000 MIPS speed processing capacity when running at full speed. Due to
the low coding efficiency of MPEG-4 video encoder transferred directly to DSP platform, it is
needed to improve the program structure, data structures and algorithms combined with
TMS320C6416T characteristics. First: Design the image storage architecture by balancing the
calculation spending, storage space cost and EDMA read time factors. Open up a more buffer in
memory, each buffer cache 16 lines of video data to be encoded, reconstruction image and
reference image including search range. By using the variable alignment mode of the DSP,
modifying the definition of structure variables and change the look-up table which occupy larger
space with a direct calculation array to save memory space. After the program structure
optimization, the program code, all variables, buffering buffers and the interpolation image
including the search range can be placed in memory. Then, as to the time-consuming process
modules and some functions which are called many times, the corresponding modules are written
in parallel assembly language of TMS320C6416T which can increase the running speed.
Besides, the motion estimation algorithm is improved by using a cross-hexagon search
algorithm, The search speed can be increased obviously. Finally, the execution time,
signal-to-noise ratio and compression ratio of a real-time image acquisition sequence is given.
The experimental results show that the designed encoder in this paper can accomplish real-time
encoding of a 768× 576, 25 frames per second grayscale video. The code rate is 1.5M bits per
second.
