An illuminator and mask patterns were optimized (SMO) to minimize CD variation of a set of contact patterns selected
from logic layouts and an array of SRAM cells. MEEF and defocus characteristics of the target patterns were modeled as
functions of constraints on minimum mask features and spaces (MRC). This process was then repeated after linearly
shrinking the input patterns by 10%. Common statistical measures of CD control worsen as MRC becomes more
restrictive, but these are weak indicators compared to behavior at points in the image that exhibit high MEEF or low
depth of focus. SMO solutions for minimum MEEF and maximum depth of focus are different, so some compromise is
necessary. By including exposure time among the variables to be optimized, some control over local mask bias is made
available to minimize MEEF and loss of litho quality due to MRC.
The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most
critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting
latent images in the wafer due to exposure of different design layouts. Accurate models can precisely
capture the proximity effects for the lithographic process and help RET engineers build the proper recipes
to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the
lithography environment that we want to model, and metrology data are collected for these geometries.
This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical
dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist
edge) data however model calibration requires EPE data for simulation. To work around this problem, only
symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements.
In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that
cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond.
The absence of 2D and asymmetric test structures in the calibration process would require models to
interpolate or extrapolate the EPE's for these structures in a real design.
In this paper we present an approach to extract the EPE information from both SEM images and contours
extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a
55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each
of these structures can be individually weighed according to the data variance. Model accuracy is then
compared to the conventional method of calibration using symmetrical data only. The paper also illustrates
the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to
errors compared to the conventional method.
Overlay variations between different layers in Integrated Circuits fabrication can result in poor circuit performance, even
worst it can cause circuit mal function and consequently affect process yield. Coupled with other lithographic process
variations this effect can be highly magnified. This leads to the fact that searching for interconnects hot spots should
include overlay variations into account. The accuracy of inclusion of the overlay variation effect comes at the expense of
a more complex simulation setup. Many issues should be taken into consideration including runtime, process
combinations to be considered and the feasibility of providing a hint function for correction.
In this paper we present a systematic approach for classification of interconnects durability through the lithographic
process, taking into account focus, dose and overlay variations, the approach also provides information about the cause
for the low durability that can be useful for building a more robust design.
This classification can be accessible at the layout design level. With this information in hand, designers can test the
layout while building up their circuit. Modifications to the layout for higher interconnects durability can be easily made.
These modifications would be extremely expensive if they had to be made after design house tape out.
We verify this method by showing real wafer failures, due to bad interconnect design, against interconnects' durability
classifications from our method.
Decreasing k1 factors require improved empirical models for the most critical challenge at 65nm node, contact holes especially. These requirements are reflected in the need for increasingly accurate lithography contour simulations. One of the major contributors to final OPC accuracy is the quality of the optical model. In this study, a new approach to the calibration of an optical model by using KIF will be proposed based upon the real through scanners and steppers of illumination distribution and implement to the OPC kernel.
As line width shrunk down to 90nm and below, resolution-enhanced technology in combination with thinner resists, higher NA (numerical aperture), OPC (optical proximity correction), and special mask types becomes essential for standard lower k1 lithography. Although DDL (double dipole) is popular for low k1 technology, separated x- and y-direction mask exposures will complex the process and reduce throughput. Quadrupole (Nikon) and QUASARTM (ASML) are well-known technologies for smaller pitch approaches with 45o circuit design ruled out constraints. In this paper, we report novel customized-illumination apertures for resolution-enhanced patterns and through-pitch critical dimensions control using a single exposure without design constraint and alignment problems. Both simulation and real exposure results are compared and the difference between aerial images and real resist profiles are also presented. Through-pitch CD uniformity, MEEF, line-end shortening, linearity, and DOF is improved for different illumination apertures with reduced OPC loading and cost effectively.
In 65nm and beyond generations, contact/via patterning is more challenging due to the complexity of manufacturing masks and the weak lithography process window. High NA scanners and suitable illumination can provide the desired resolution and dense pitch. However, there are trade-offs between process window, mask error enhancement factor (MEEF), and proximity effect. Some assistant technology is reported in literature, such as thermal flow, RELACS, SAFIER and sub-resolution assistant features. In this paper, we report a detailed study of the feasibility and limitations of these kinds of methods. Finally, we describe sub-resolution assistant features when used in QUASAR illumination with lower sigma, which have shown great promise to reduce the proximity effect and MEEF to get a larger lithography process window.
Shrinkage technologies have attracted much more attention recently. The main shrinkage techniques are either to generate a thermal flow in the photo-resist with a high-temperature baking process, or to form a top layer with mixing bake treatment. In this paper, United Microelectronics Corporation (UMC) introduces a new shrinkage technology called MCTP (multiple Chemical Trim Process) and present the experimental results for our evaluation of the MCTP to implement the 90nm gate layer. Furthermore, this paper focuses on the correlation between developer process and mixing bake treatment, which has greatly benefits process window and leads to good line-edge roughness (LER) performance, especially for line-end shortening.