The readout chain circuits for time delay integration charge coupled device camera imaging system include CCD focal plane driving circuit, analog-to-digital conversion circuit, high-speed digital data transmission circuit and other parts together. The parasitic factors such as the quality of high frequency clock, high speed data transmission error rate and the aging of printed circuit board will induce more noise to image data of camera. As the longer time circuits working, the noise of readout chain becomes bigger and bigger, then the signal-to-noise becomes worse. This paper proposed a method to make circuit system check its noise as the circuit is working, which is based on pseudo CCD-signal to check the Signal-to-Noise of readout chain of TDICCD, and sends the result to control core of the system. The paper combines the theory calculation and actual measurement as the method for testing. High precision pseudo CCD signal source is used to test the onboard circuit and circuit SNR results of readout chain, harmonic frequency, noise floor and other related parameters are automatic processed.
At present, single-slope analog-to-digital convertor (ADC) is widely used in the readout circuits of CMOS image sensor
(CIS) while its main drawback is the high demand for the system clock frequency. The more pixels and higher ADC
resolution the image sensor system needs, the higher system clock frequency is required. To overcome this problem in
high dynamic range CIS system, this paper presents a 12-bit 500-KS/s cyclic ADC, in which the system clock frequency
is 5MHz. Therefore, comparing with the system frequency of 2N×fS for the single-slope ADC, where fS, N is the
sampling frequency and resolution, respectively, the higher ADC resolution doesn’t need the higher system clock
frequency. With 0.18μm CMOS process, the circuit layout is realized and occupies an area of 8μm×374μm. Post
simulation results show that Signal-to-Noise-and-Distortion-Ratio (SNDR) and Efficient Number of Bit (ENOB) reaches
63.7dB and 10.3bit, respectively.
A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit
asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low
power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high
bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit