Range pattern matching with layer operations and continuous refinements

I-Lun Tseng; Zhao Chuan Lee; Yongfu Li; Valerio Perez; Vikas Tripathi; Jonathan Yoong Seang Ong

doi:10.1117/12.2297351

20 March 2018 Range pattern matching with layer operations and continuous refinements

I-Lun Tseng, Zhao Chuan Lee, Yongfu Li, Valerio Perez, Vikas Tripathi, Jonathan Yoong Seang Ong

Proceedings Volume 10588, Design-Process-Technology Co-optimization for Manufacturability XII; 105880J (2018) https://doi.org/10.1117/12.2297351
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

At advanced and mainstream process nodes (e.g., 7nm, 14nm, 22nm, and 55nm process nodes), lithography hotspots can exist in layouts of integrated circuits even if the layouts pass design rule checking (DRC). Existence of lithography hotspots in a layout can cause manufacturability issues, which can result in yield losses of manufactured integrated circuits. In order to detect lithography hotspots existing in physical layouts, pattern matching (PM) algorithms and commercial PM tools have been developed. However, there are still needs to use DRC tools to perform PM operations. In this paper, we propose a PM synthesis methodology, which uses a continuous refinement technique, for the automatic synthesis of a given lithography hotspot pattern into a DRC deck, which consists of layer operation commands, so that an equivalent PM operation can be performed by executing the synthesized deck with the use of a DRC tool. Note that the proposed methodology can deal with not only exact patterns, but also range patterns. Also, lithography hotspot patterns containing multiple layers can be processed. Experimental results show that the proposed methodology can accurately and efficiently detect lithography hotspots in physical layouts.

Conference Presentation

Citation Download Citation

I-Lun Tseng, Zhao Chuan Lee, Yongfu Li, Valerio Perez, Vikas Tripathi, and Jonathan Yoong Seang Ong "Range pattern matching with layer operations and continuous refinements", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880J (20 March 2018); https://doi.org/10.1117/12.2297351

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