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The paper considers results of design and simulation of continuously logical cells (CLC) based on current mirrors (CM) with functions of preliminary analogue processing for image intensity transformation and coding for construction of mixed image processors (IP) and neural networks (NN). For such IP and NN with vector or matrix parallel inputsoutputs, it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such CLC has a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of CLC variants for photocurrents transformation and coding and their various possible implementations and simulations. The basic element of such cells is a scheme that implements the operation of a bounded difference of continuous logic. Using a set of such circuits implemented on traditional CMOS technology, we consider generalized decomposition and other methods for designing cells for nonlinear conversion of the photocurrent intensity, which makes it easy to realize the required nonlinear conversion function. Selection of the appropriate parameters, which can be specified as constructive constants or as parameters for external control, allows changing type of synthesized functions. We also consider the applications of such parallel matrix arrays for the creation of advanced IP and NN. We show the need for various types of converting and coding the photocurrents intensity in such parallel systems and sensory devices, especially for the implementation of various types of activation functions in the hardware implementations of neural networks. Such cells consist of several dozen CMOS transistors, have low power supply voltage (1.8 ÷ 3.3V), the range of an input photocurrent is 0.1÷24μA, the transformation time is less than 1 μs, low power consumption (microwatts). We also consider the cells for ADC after the intensity conversion. Each channel consists of several digital-analog cells (DC). The amount of DC is not exclusive to the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC and SHD, and it has only 35 CMOS transistors. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. The ADCs with 6-8 bit binary or Gray codes have good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 10MHz and more). In such ADCs, easily parallel code can be realized. The circuits and the simulation results of their design with OrCAD are shown. The CLC and ADC on current mirrors open new prospects for realization of linear and matrix IP and NN with MIMO-operands.
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