2.

CCD STRUCTURE

The pixel architecture used for TDI-CMOS charge domain (or qTDI) is represented in Figure 1. It is a 4 phase CCD structure with minimum poly-poly gap (0.25μm). The pixel is bi-directional with identical output ports at either end of the CCD structure. This structure is based on a buried channel implantation to achieve good charge transfer efficiency (CTE) and to minimize post radiation degradation as seen with surface channel approach [1].

Figure 1

Pixel schematic and 3D structure.

The clocking of the CCD phases is overlapping as shown in Figure 2. The transfer direction can simply be changed by swapping two of the clocks. This feature is accessible via an SPI interface. Gate voltage and clock slew rate are optimized for best full well capacity and CTE trade-off.

Figure 2:

CCD structure phase clocking.

The clock generator and drivers are embedded in the chip greatly simplifying the integration of this detector. Note that careful lay out technics are used to obtain correct clock slew rate and avoid IR drops due to current demand during switching activity.

3.

PROTOTYPE EVALUATION

A prototype, see Figure 3, was developed to test CCD structure variants with 2 pixel pitches of 5 and 10 μm. This prototype was designed to not only prove the pixel technology but also a periphery to support high line rate up to 300klines/s. The image area is composed of a single TDI-CCD structure of 4096 columns with 256 or 64 TDI stages depending on the pixel pitch. In order to achieve this line rate of up to 300 klines/s a very fast single slope 12 bits ADC technique has been developed and implemented. The 12 bits conversion is achieved in 0.9μs. The classic single slope ADC architecture was modified to work around a counter generating eleven Gray code bits and three phase-shifted clocks providing 12 bits output (see Figure 4) in total at very high line rates:

The complete column readout path is illustrated in Figure 5.

The data resulting of the image conversion is then sent to a gigabit transmitter (GTX) composed of a serializer working in double data rate mode (DDR) at 3.6GHz and a CML (3.6Gb/s) data driver. A high speed CML output driver has been selected to minimize the number of output ports to simplify the interface to the data capturing device. Input signals such as clock, integration control and SPI interface use LVDS format.

The CCD-structure clock drivers require attention and floor planning, see Figure 6:

Figure 3

Die design prototype

Figure 4

Example of timing access to the sensor CIS125.

Figure 5

High speed ADC readout diagram and timing.

Figure 6

CCD structure phase clocking.

4.

PROTOTYPE DEVICE EXPERIMENTAL RESULTS

4.2

Electro-optical performance

The implementation of good CCD structure in CMOS represents several challenges of which the two mains ones are obtaining good CTE and high enough full well capacity. In that respect and compared to CCD the limitations of CMOS technology to be overcome are non-overlapping poly gates and lower supply voltages. The former affects the CTE and the later the FWC. In addition and similar to CCD technology a surface channel CCD structure although giving higher full well will suffer from high CTE degradation end of life (EOL) worsening drastically MTF performance. This is because trap generated at the silicon surface will trap and release electron at different clock phases. Hence all the CCD structure pixels use buried channel architecture despite the loss of Full Well. An advantage of the buried implant is that it reduces the potential pockets of poly-poly gap (0.25μm). In order to overcome the lower supply voltage of CMOS technology negative supplies are used to increase the potential across each pixel. It can be noted that summing in the digital domain two of the CCD structure, also called sub-TDI arrays is recommended to increase the signal noise ratio. This is because while the total charge is added in a linear fashion the noise is added in root square fashion only.

A summary of the main results are given below and can be found in more details in [1]. On a 5μm pitch CCD structure with anti-blooming a FWC of 30ke- was measured with a CTE better than 0.99999. The signal non-linearity achieved is less than 2%, while the dark current performance is 3.7 nA/cm² with a temperature doubling factor of 9.5°C. The Arrhenius plot indicates an activation energy (E_a) of 0.6eV. This corresponds to half the silicon band gap confirming that the dark current source is the conventional Shockley-Read-Hall (SRH) mechanism. The charge conversion efficiency graph shows a pixel conversion gain of 35μV/e-. This gain is designed to optimise noise floor versus full well and hence dynamic range.

Figure 7

Left CTE measurements and right Photon Transfer Curve.

Figure 8

Dark current.

4.4

CCD structure

For the CCD structure the concerns are mainly around two parameters, dark current (including bright pixel) and CTE performance degradation when subject to Gamma and proton radiation. The results [4] below show a good behaviour with acceptable results for a flight mission.

The Gamma radiation increased the dark signal of the Non-Anti-bloomed (AB) split by a factor 2 at 30krad while the AB split was more affected (x2.5). This is explained by the fact that AB split has less STI and less active area but has more gate edges and poly gaps (Non-continuous poly gates). A similar observation is made after the proton irradiation, see table for details. The higher increase for the AB splits is also explained by the higher level of gate edges.

Figure 9

Post radiation dark current: Left is post Gamma and 7 days room temperature anneal; right is post Proton and 14 days room temperature anneal.

Figure 10

Bright pixel post proton and 14 days room temperature anneal.

Table 2

Dark current summary at 30krad and 5x1010 p/cm2 Proton exposure.

	Pre-radiation	Post Gamma 30krad	Post proton - 5x1010 p/cm2
Without AB	3-4nA/cm2	< x2	<x3
With AB	3-4nA/cm2	~x2.5	<x4

The results below show a very small and similar CTE degradation of both the AB and non-AB versions of the prototype device with Gamma and proton up to doses that would be expected in typical space based applications

Figure 10

CTE versus Proton fluence (left) and Gamma dose (Right).

Single Event Effect (SEE)

Usually, the SEE is categorized in:

• • Non-destructive

  • • Single event upset (SEU) – change of logic state in memory element.

  • • Single event transient (SET) – transients in circuit that lead to erroneous data being captured.

  • • Single event functional interrupt (SEFI) – temporary loss of device functionality (for an imager of this simplicity, this is caused by bus contention).

• • Potentially Destructive

  • • Single event latch-up (SEL) – a parasitic thyristor causes circuit lockup or catastrophic failure.

Teledyne has developed design rules and layout rules that have secured several projects such as MTG or METImage giving high immunity to heavy ion. These results have been reported in details at the ICSO conference 2016 and below is a summary table.

Table 3

MTG-FCI results 3.

	LETth (MeVcm2mg-1)	Mission rate (day-1)	Reliability over 8.5 years (%)	Comments
SEL	> 67.7	< 2x10-6	99.2	This worst case as no latch-up was actually observed
SEU rad-hard register	65	< 4x10-12	99.9999	Sequencer, timing and readout control
SEU low power register	19	< 1x10-8	99.996	Serial programmable interface

5.

NEXT ACTIVITIES

The technology described in this paper is now being used to make a prototype full sized TDI CMOS image sensor called the CIS125 in a program funded by the UK Space Agency (CEOI). The architecture developed is shown Figure 11. This qTDI detector is composed of 4 panchromatic (PAN) bands and 8 multi-spectral (MS) bands. The configuration reported here is optimised for the CEOI program and each PAN and MS are composed of sub-TDI bands (A&B) that enhance the full well by adding digital summation to the charge domain performance. The PAN and MS number of TDI lines were carefully chosen to optimise application needs versus silicon area. Each sub-TDI needs to be read out separately and therefore needs its own conversion. This is the equivalent of reading out 16 independent bands.

Figure 11

Sensor Architecture

This sensor is a stitched device of 16k columns for the PAN and 8k columns for the MS. The pixel is 5μm and 10μm for the PAN and MS respectively, see Table 4. The high speed ADC per column described earlier allows a line rate of up to 14kHz if all of the sensor lines and sub lines are read. A single read path is shared between all bands enabling the implementation of a maximum number of bands without the need of 2D stitching technology and optimising power consumption.

Table 4

Configuration for CEOI program.

The number of TDI stages per bands are selectable as follow:

This sensor will be made with a 0.18μm Imaging CMOS process using thick and high resistivity epitaxial silicon. The device is also back-illuminated to improve fill factor and it will be thinned (using Teledyne-e2v process) to optimise QE versus MTF. To enhance further it performance an Anti-reflection coating will be deposited as well as black-coating between channels to avoid straight light effects.

CIS125 is designed as a modular platform to enable to adapt to a wide range of configuration with lower risk associated to new development.

6.

SUMMARY

A TDI-CMOS sensor for high resolution earth observation has been presented:

In this paper has also presented the performance of the CCD structure used and demonstrated high TRL level:

This technology has now reached a maturity where full sensors are being design for flight applications and example is give showing the type of architecture that is possible in a full sensor design