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For 28 nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as sub-resolution assist features (SRAF), litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning(SAQP), and source-mask optimization (SMO) are utilized for the low k1 factor lithography processes. The litho-to-etch pattern fidelity is extremely critical since a slight lithography pattern weakness (ex: photoresist (PR) thickness loss, profile roughness ...) may be worsened after etch process due to the pattern loading effect, which will then induce physical defects that affect the final electrical performance. Rigorous lithography simulation can provide a reference of pattern weaknesses to modify mask layouts; but it is incapable of full-field mask data preparation. The post-etch critical dimensions (CDs) with a high accuracy optical proximity correction (OPC) model has become an important component; but it requires massive wafer data of post-litho and post-etch CDs, and will increase the runtime of the OPC flow for OPC modelers. In our previous submission [1-2], we had brought forth an algorithm that utilizes multi-intensity levels from conventional aerial image simulations to assess the physical profile through lithography to etch steps, and proposed a novel litho-etch correction method without suffering the lithography process window of SADP process. In this paper, we have improved this methodology and introduced a new approach of virtual etch target (VET) with virtual etch target threshold to assess post-etch CDs for various applications of memory patterning (dense features by SADP or SAQP process) and logic patterning (random features of lines, trenches and holes) more efficiently. The results not only matched post-etch wafer data, but also agreed with post-etch process window. Furthermore, this methodology can be utilized in generic OPC and post-OPC verification procedures to improve final pattern fidelity for logic and memory products.
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