BOPA: a traffic planning algorithm for minimizing buffer resources for onboard TSN switching

Jinfeng Huang; Zhenjiang Long; Wenwen Fu; Zhigang Sun

doi:10.1117/12.2628720

7 March 2022 BOPA: a traffic planning algorithm for minimizing buffer resources for onboard TSN switching

Jinfeng Huang, Zhenjiang Long, Wenwen Fu, Zhigang Sun

Proceedings Volume 12167, Third International Conference on Electronics and Communication; Network and Computer Technology (ECNCT 2021); 121672A (2022) https://doi.org/10.1117/12.2628720
Event: 2021 Third International Conference on Electronics and Communication, Network and Computer Technology, 2021, Harbin, China

Abstract

TSN(Time-Sensitive Networking) can provide deterministic switching services for critical traffic, which is an important development trend of onboard switching. Traffic planning is the key to onboard TSN applications. Its function is to map critical traffic to specific time slots in the network for transmission. Different planning results will cause different buffer requirements. FPGA-based TSN switch customization is an important way for onboard switch design. Minimizing switch buffer resources is of great significance to reducing FPGA size and power consumption. Based on the backtracking idea, this paper proposes a planning algorithm, named BOPA (Buffer size Optimized Planning Algorithm), to minimize the buffer size of the TSN switch. Simulation results show that BOPA can obtain the minimum value of TSN switch buffer resources according to the scene requirements under the premise of determining the topology and load.

Citation Download Citation

Jinfeng Huang, Zhenjiang Long, Wenwen Fu, and Zhigang Sun "BOPA: a traffic planning algorithm for minimizing buffer resources for onboard TSN switching", Proc. SPIE 12167, Third International Conference on Electronics and Communication; Network and Computer Technology (ECNCT 2021), 121672A (7 March 2022); https://doi.org/10.1117/12.2628720

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