A high power supply rejection LDO with feed-forward ripple cancellation

Zhichao Lu; Shengming Huang; Quanzhen Duan

doi:10.1117/12.2639114

15 July 2022 A high power supply rejection LDO with feed-forward ripple cancellation

Zhichao Lu, Shengming Huang, Quanzhen Duan

Proceedings Volume 12258, International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022); 122582G (2022) https://doi.org/10.1117/12.2639114
Event: International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022), 2022, Qingdao, China

Abstract

In this design, a 0.35um BCD process is used to design a high power supply rejection ratio LDO with feed-forward ripple elimination. By analyzing the power supply noise interference, a feed-forward ripple elimination circuit is used to reduce the power supply noise on the output. In order to ensure that the LDO has a high power supply rejection ratio in a wide load range, the output voltage of the LDO is 1.8V, the input voltage range is 2.5V to 5V, the load current range is 0 to 20mA, and the quiescent current is less than 80μA. The simulation results show that when the input voltage is 5V, the PSRR at low frequency at no load is 114dB, and the PSRR at 10 kHz is 77dB; when the load is 20mA, the PSRR at low frequency is 104dB, and the PSRR at 10 kHz is 72dB.

Citation Download Citation

Zhichao Lu, Shengming Huang, and Quanzhen Duan "A high power supply rejection LDO with feed-forward ripple cancellation", Proc. SPIE 12258, International Conference on Neural Networks, Information, and Communication Engineering (NNICE 2022), 122582G (15 July 2022); https://doi.org/10.1117/12.2639114

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