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1.INTRODUCTIONOscillator (OSC) is an important part of many electronic systems and is widely used in various electronic devices1, 2. With the expansion of application scope and the development of integrated circuit, the demand for high-performance OSC circuit is higher and higher, which has also become an important research topic3. The design difficulty of OSC circuit lies in the balance and compromise of many performances such as low voltage, high precision and low power consumption4, 5. Ring oscillator has become the most commonly used structure because of its feedback regulation, relatively high precision and simple implementation6. In the existing ring OSC circuit, because the clock cycle is related to the delay, and the delay is greatly affected by the process and temperature, resulting in large frequency deviation7, poor stability and low circuit accuracy, which cannot fully meet the requirements of the system for high-performance OSC circuit. Generally, in P, T and V simulation, it is difficult to control the output frequency deviation of OSC within ± 10%, let alone ± 5%. Based on this, a low-voltage, low-power and high-precision ring ICO circuit structure is proposed in this paper. 2.TRADITIONAL RING VOLTAGE CONTROLLED OSCILLATOR CIRCUITAs shown in Figure 1, the traditional ring voltage controlled oscillator (VCO) mainly includes current source circuit, RC circuit, operational amplifier circuit (OPA), VCO and other circuit structures8. Its main working process is as follows: the current source provides currents IBIAS1 and IBIAS2 for RC circuit and OPA respectively; The resistance R branch in the RC circuit provides the reference voltage VR for the lower OPA; The capacitor C branch completes the charging and discharging process alternately under the control of the ordinary switch, and takes the voltage on it as the input VC at the other end of the OPA; The voltages VR and VC are differentially amplified by the OPA to obtain the voltage V0; In VCO, the output clock signal Fout is converted; In addition, the output clock will feed back to control the operation of the current source and RC circuit, so as to realize the circuit feedback control9. The frequency value is: In the above equation, Under the starting state and normal working state of this circuit, the current demand of the system is different, and the working condition of MOS transistor is different. If it is not distinguished, the power consumption and accuracy performance of the circuit will deteriorate; Secondly, the common switch controlled by the digital logic circuit will have the risk of leakage, and in the VCO circuit, when the power supply voltage is low, the output voltage range of the OPA is narrow, resulting in the limited output frequency range of the circuit, which will seriously deteriorate the accuracy of the system and even cause the circuit to stop vibration. To sum up, this circuit has defects in accuracy, power consumption and other performance. 3.HIGH PRECISION ICO CIRCUIT3.1Overall architectureBased on the traditional ring VCO circuit, the structure proposed in this paper introduces circuit modules such as bootstrap switch, counter and specially designed ICO controlled by special timing, so as to greatly improve the circuit performance and make it can be used in low-voltage, low-power and high-precision places. The specific architecture is shown in Figure 2, the current source acts on the resistance to form the reference voltage VR, and VR = Iref ∗ R1. On the other hand, the current source charges capacitor C2 to form voltage VC. C1 and C3 are voltage stabilizing capacitors. Its working process is: When VR > VC, the charge obtained by the capacitor C2 through the current source is less than the charge discharged by the circuit through the capacitor C2, the output voltage of the OPA decreases, the current value obtained by ICO decreases, the charging time of the circuit becomes longer, and the output clock frequency decreases. After circuit feedback, the on-off frequency of the Control RC circuit decreases, and more charge will be charged on the capacitor C2, which increases VC and plays the role of negative feedback; Similarly, when VR < VC, the charge obtained by the capacitor C2 through the current source is greater than the charge discharged by the circuit through the capacitor C2, the output voltage of the OPA increases, the current value obtained by ICO increases, the charging time of the circuit shortens, and the output clock frequency increases. Through the circuit feedback control, the switching frequency of the RC circuit increases, and the charge charged on the capacitor C2 will decrease, thus reducing VC. The circuit constantly changes between these two states to form a stable clock signal. Here, the amount of charge obtained by C2 from Iref is equal to the amount of charge released from C2, i.e.: Thus there: So the values of C1 and C2 can be calculated; The resistance with the smallest deviation with temperature change is constructed by temperature compensation, and the capacitance with the best temperature coefficient is used as C2, and the device with the largest unit capacitance is used as C1. The OPA uses a common source and common gate structure, and the offset needs to be considered in the design process. In order to enhance the loop stability of the circuit, the gain value of the circuit needs to be controlled reasonably; Considering the reasonable size of input tube and load tube, the gain value of input tube must be greater than that of load tube. In this circuit, a counter is introduced to control the operation of the current source module. In the initial stage of the circuit, a relatively high bias current is provided for the OPA to reduce the establishment time of the OPA, and reduce the current after the normal operation of the circuit, so as to reduce the power consumption; By adopting the bootstrap switch circuit controlled by special timing, the accuracy of the circuit will be greatly improved and the circuit can work at a lower power supply voltage; In addition, the output frequency range of the circuit is widened through ICO structure to improve the accuracy and speed of the circuit. 3.2Design of counterThe counter circuit is composed of D flip-flop. Its main function is to count the output clock of OSC to realize the delay function. As shown in Figure 2, on the one hand, the counter controls the current source to reduce power consumption, on the other hand, it controls the operation of switch SW1 and switch SW2 to increase speed and accuracy. Firstly, the counting result will control the output current value of the current source circuit and provide large current to the OPA at the beginning of power on, so as to meet the demand for large current when the feedback loop looks for and adjusts the circuit working point, so as to reduce the loop stability time. After the circuit works stably, that is, after the counting is completed, the demand for large bias current of the whole circuit decreases, and then reduce the output value of the current source, so as to reduce the power consumption. Secondly, during normal operation, the current sources IBIAS1a and IBIAS1b alternately provide current for the branches where R1 and C2 are located under the control of switch SW1 and switch SW2 to realize the chopping function. The chopping structure of the current source is used to eliminate the influence of the difference between the current sources IBIAS1a and IBIAS1b on the output frequency. However, if the capacitor charging process is not over, the two current sources are exchanged, which will introduce the error of the capacitor branch into the resistance branch and reduce the circuit accuracy. Because before VC is not stable, the current in the branch where resistor R1 is located is different from that in the branch where capacitors C2 and C3 are located, and the current source tube supplying power to C2 and C3 branches initially works in the unsaturated area. At this time, the current of C2 and C3 branches is 0 and the current of R1 branch is IBIAS1. At this time, if the current sources of two branches are exchanged, a transition period will occur and the voltage VR on the resistance will be unstable, and VR is used as the reference voltage of the whole circuit. If instability occurs, it will eventually lead to the instability of the whole loop, which will seriously affect the accuracy of the circuit. In addition, the power on speed of the OPA is often slower than the charging speed of the RC circuit. If special treatment is not carried out, the working state mismatch will occur among the current source circuit, RC circuit and OPA. Therefore, the structure controls the working conditions of switch SW1 and switch SW2 through the counter, so that the circuit nodes will not exchange current sources before reaching the working voltage, so as to avoid the power on error of each branch of the circuit, especially the capacitor branch and OPA, being introduced into the OSC and affecting the accuracy of the whole circuit. 3.3Design of bootstrap switchThe bootstrap circuit uses the characteristics of capacitor storage charge to realize boost. As the core circuit of the OSC, C2 branch in Figure 2 is very sensitive to leakage, so the conductivity and leakage of the control switch will be very helpful to improve the circuit accuracy and reduce the circuit power consumption. This structure uses the special timing control signal shown in Figure 3 to assist the operation of the bootstrap switch, which can not only improve the accuracy of the circuit, but also make the circuit work at a lower power supply voltage. Figure 3 shows the three control signals outn_d, outn and outp timing diagram, in this way, multiple complementary overlapping clocks can be constructed. The specific working process is as follows: in Figure 2, in the first half cycle, outp= 0, outn= 1, outn_ d= 1, M1 tube is on, M2 tube is off, M3 and M4 tube is on, M5 tube’s gate voltage is 0, M5 tube is off, and M2 tube’s drain voltage value is VDD; In the second half of the cycle, outp= 1, outn= 0, outn_ d=0, M1 tube turns off, M2 tube turns on, M3 and M4 tube turns off. Under the action of C5, the gate voltage of M5 tube is VgM5 = VDD + outp, which improves the conductivity of M5 tube. Using multiple complementary overlapping clocks and working with the bootstrap switch in the design can not only reduce the overshoot and improve the continuity of the switch, but also ensure that M4 tube and M5 tube will not be connected at the same time, so as to reduce the frequency deviation caused by the additional discharged charge due to leakage and improve the accuracy of the OSC. 3.4Design of ICO circuitFigure 4 shows, the gate voltage VIN of M6 is the output voltage of the OPA. C4 filters this voltage to reduce interference. During operation, IM6 changes with the change of VIN, and through the current mirror image of M7 and M8 tube, together with the current IBIAS3, finally forms the current of M9 tube IM9 =IM6 - IBIAS3. Thus, the transformation from voltage to current is realized, and then the current is transformed into output clock by controlling the operation of the ring inverter with this current. Although the output range of the OPA is narrow, the current range that can be controlled is very wide, so the current range supplied to the ICO circuit is very wide, which widens the output frequency range of the circuit and makes it match the frequency range corresponding to the previous RC circuit, which greatly improves the accuracy of the system; On the other hand, the introduction of current source makes the current of the whole circuit limited and the power consumption controllable. In the design, it is necessary to consider the matching of gm of M6 and the later IBIAS3 on the control ability of frequency F, that is, the ability to change from VIN to IBIAS3 and from IBIAS3 to F need to be matched with each other, otherwise the stability and regulation ability of the loop will be affected. Figure 4 shows, its core components are the ring inverter composed of an odd number of inverters whose current is controlled by IM12 and IM13, and the output circuit for shaping. When the frequency is high, the range of voltage VB at the output terminal B of the ring inverter is not VDD-VSS, but V1-V2, and VSS < V2 < V1 < VDD. Ideally, M12 tube and M13 tube are completely symmetrical, and V1-VSS = VDD-V2. However, in the actual design, VB is very sensitive to mismatch, and the offset will lead to the deviation of VB voltage range, resulting in the non operation of M16 and M17. In order to solve this problem, on the one hand, WM13 = 2WM12 is set in this structure, so that IM12 ≠ IM13, that is, the influence of device mismatch on the circuit becomes insignificant by deliberately pulling the working state sharply, so as to eliminate the influence of offset on the circuit. At this time, the voltage range of VB shifts towards VSS as a whole. In addition, because the circuit is no longer sensitive to mismatch, the size of each tube in this module can be relatively small to reduce the circuit parasitic, so as to further improve the circuit accuracy. C6 is used to realize voltage stabilizing and filtering. On the other hand, capacitor C7 is introduced to improve the working state of M16 and M17 tube and improve the circuit accuracy. Capacitor C7 can not only realize isolation and prevent the jitter of clkout end from being coupled to the gate of M16, so that the gate voltage between M16 tube and M17 tube is relatively independent; It can also complete the charge transfer, superimpose VB on the DC level, improve the conductivity of M16 tube, improve the inconsistency of M16 and M17 conductivity caused by the overall downward deviation of VB, improve the duty cycle of Vout and reduce the design difficulty of M16 tube and M17 tube. Among them, for VA: From equation (5), it can be seen that when the coupling capacitance increases, ZC decreases, resulting in the increase of VA. the final design takes the coupling capacitance as 320fF. In addition, the current source provides bias for point A. on the one hand, it provides DC level for point A, on the other hand, it makes its current value change synchronously with the system, so as to ensure the smooth progress of loop regulation process. 4.TEST RESULTSThe chip is manufactured by 0.18 μm CMOS process. When VDD = 0.67V and the temperature is - 40°C -125°C, five chips are tested, and the test results are shown in Table 1. All deviations in Table 1 are calculated based on the situation at 27°C. Table 1.Variation of output frequency with temperature.
It can be seen from Table 1 that the variation deviation of output clock with temperature is within ± 2.5%. When the temperature is 27 °C, and VDD is 0.6V-0.9V, the test results of five chips are shown in Table 2. Table 2.Variation of output frequency with power supply voltage.
All deviations in Table 2 are calculated based on the power supply voltage VDD = 0.77V. It can be seen from Table 2 that the variation deviation of output clock with power supply voltage is within ± 1%. 5.CONCLUSIONThe ring ICO circuit structure proposed in this study greatly improves the temperature characteristics and power supply characteristics on the basis of the traditional ring VCO circuit through the cooperation of the counter, the bootstrap switch with special timing control and the special ICO circuit module, so as to obtain a high-precision output clock in the application environment of low supply voltage, and the power consumption of the module is very low. Through testing, the performance of the chip was also verified, and when the voltage was 0.77V and the output frequency was 1.32MHz, the output clock changed with temperature to within ±2.5%, and with the voltage change was within ±1%, and the power consumption was only 382nw. REFERENCESRavezzi, L.,
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