Poster + Paper
26 November 2023 A high-throughput and FPGA-based LDPC decoder for continuous-variable quantum key distribution system
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Conference Poster
Abstract
The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Chuang Zhou, Yang Li, Li Ma, Yujie Luo, Jie Yang, Mei Wu, Shuai Zhang, Wei Huang, and Bingjie Xu "A high-throughput and FPGA-based LDPC decoder for continuous-variable quantum key distribution system", Proc. SPIE 12775, Quantum and Nonlinear Optics X, 1277517 (26 November 2023); https://doi.org/10.1117/12.2687070
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KEYWORDS
Field programmable gate arrays

Continuous variable quantum key distribution

Matrices

Clocks

Quantum systems

Quantum security

Signal to noise ratio

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