Realization of a neuronal hardware with digital signal processor and programmable gate arrays

Anke Meyer-Baese; Uwe Meyer-Baese; Henning Scheich

doi:10.1117/12.205092

6 April 1995 Realization of a neuronal hardware with digital signal processor and programmable gate arrays

Anke Meyer-Baese, Uwe Meyer-Baese, Henning Scheich

Proceedings Volume 2492, Applications and Science of Artificial Neural Networks; (1995) https://doi.org/10.1117/12.205092
Event: SPIE's 1995 Symposium on OE/Aerospace Sensing and Dual Use Photonics, 1995, Orlando, FL, United States

Abstract

In this paper we describe how the processing speed of a radial basis neural network can be performed by the use of field programmable gate arrays (FPGA). The calculation of the very time-consuming exponential function is taken by an optimized CORDIC-processor. We determine the number of the necessary FPGAs and do a processing speed comparison between FPGA and DSP referring to an application in speech recognition.

Citation Download Citation

Anke Meyer-Baese, Uwe Meyer-Baese, and Henning Scheich "Realization of a neuronal hardware with digital signal processor and programmable gate arrays", Proc. SPIE 2492, Applications and Science of Artificial Neural Networks, (6 April 1995); https://doi.org/10.1117/12.205092

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