Design of a dataway processor for a parallel image signal processing system

Mitsuru Nomura; Tetsuro Fujii; Sadayasu Ono

doi:10.1117/12.206741

21 April 1995 Design of a dataway processor for a parallel image signal processing system

Mitsuru Nomura, Tetsuro Fujii, Sadayasu Ono

Proceedings Volume 2501, Visual Communications and Image Processing '95; (1995) https://doi.org/10.1117/12.206741
Event: Visual Communications and Image Processing '95, 1995, Taipei, Taiwan

Abstract

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Citation Download Citation

Mitsuru Nomura, Tetsuro Fujii, and Sadayasu Ono "Design of a dataway processor for a parallel image signal processing system", Proc. SPIE 2501, Visual Communications and Image Processing '95, (21 April 1995); https://doi.org/10.1117/12.206741

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