DSP acceleration using cache logic FPGAs

Joel Rosenberg

doi:10.1117/12.221342

19 September 1995 DSP acceleration using cache logic FPGAs

Joel Rosenberg

Proceedings Volume 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing; (1995) https://doi.org/10.1117/12.221342
Event: Photonics East '95, 1995, Philadelphia, PA, United States

Abstract

Stand-alone digital signal processors (DSPs) support many on-chip functions and are highly optimized for the demands of high-speed computing. The problem associated with this functional optimization is that the increase in performance comes at the expense of flexibility. To make the DSP general purpose enough for a wide variety of applications, a custom ASIC must be used to achieve the desired performance. DSPs and ASICs are not able to easily adapt on-the-fly to different algorithms. Even DSPs that can do this don't match the high level of optimization provided by an ASIC. Recent developments in FPGA design tools enable system designers to develop in-system reconfigurable adaptive DSP hardware. Designed to exploit register rich, dynamically recongigurable field programmable gate arrays, high speed custom DSP functions can be created and implemented, resulting in significantly improved performance for compute-intensive applications, including graphics and image processing, telecommunications, networking and instrumentation.

Citation Download Citation

Joel Rosenberg "DSP acceleration using cache logic FPGAs", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); https://doi.org/10.1117/12.221342

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