FPGA implementation of polynomial evaluation algorithms

Milos D. Ercegovac; Jean-Michel Muller; Arnaud Tisserand

doi:10.1117/12.221338

19 September 1995 FPGA implementation of polynomial evaluation algorithms

Milos D. Ercegovac, Jean-Michel Muller, Arnaud Tisserand

Proceedings Volume 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing; (1995) https://doi.org/10.1117/12.221338
Event: Photonics East '95, 1995, Philadelphia, PA, United States

Abstract

The most significant digit first function evaluation method (E-method) allows efficient evaluation of polynomials and certain rational fucntions on custon hardware. The time required for the computation is of the order of m carry-free addition operations, m being the number of digits in the result. We discuss a digit-parallel and a digit-serial implementation of this method on a DecPeRLe-1 board, made up with Xilinx FPGAs. After a presentation of the E-method, we give a discription of the architecture of the DecPeRLe-1 board, present our designs and analyze their performances.

Citation Download Citation

Milos D. Ercegovac, Jean-Michel Muller, and Arnaud Tisserand "FPGA implementation of polynomial evaluation algorithms", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); https://doi.org/10.1117/12.221338

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