Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors

Roger Panicacci; Bedabrata Pain; Zhimin Zhou; Junichi Nakamura; Eric R. Fossum

doi:10.1117/12.236120

25 March 1996 Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors

Roger Panicacci, Bedabrata Pain, Zhimin Zhou, Junichi Nakamura, Eric R. Fossum

Proceedings Volume 2654, Solid State Sensor Arrays and CCD Cameras; (1996) https://doi.org/10.1117/12.236120
Event: Electronic Imaging: Science and Technology, 1996, San Jose, CA, United States

Abstract

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 micrometers pitch in a 1.2 micrometers n-well CMOS process and a 40 micrometers pitch in a 2 micrometers n-well CMOS process. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 (mu) W at a 5 KHz conversion rate.

Citation Download Citation

Roger Panicacci, Bedabrata Pain, Zhimin Zhou, Junichi Nakamura, and Eric R. Fossum "Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors", Proc. SPIE 2654, Solid State Sensor Arrays and CCD Cameras, (25 March 1996); https://doi.org/10.1117/12.236120

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