Fractal engine

Omid Fatemi; Sethuraman Panchanathan

doi:10.1117/12.263529

17 January 1997 Fractal engine

Omid Fatemi, Sethuraman Panchanathan

Proceedings Volume 3021, Multimedia Hardware Architectures 1997; (1997) https://doi.org/10.1117/12.263529
Event: Electronic Imaging '97, 1997, San Jose, CA, United States

Abstract

Visual media processing is becoming increasingly important because of the wide variety of image and video based applications. Recently, several architectures have been reported in the literature to implement image and video processing algorithms. They range from programmable DSP processors to application specific integrated circuits (ASICs). DSPs have to be software programed to execute individual operations in image and video processing. However they are not suitable for real-time execution of highly compute intensive applications such as fractal block processing (FBP). On the other hand, dedicated architectures and ASICs are designed to implement specific functions. Since they are optimized for a specific task, they cannot be used in a wide variety of applications. In this paper, we propose a parallel and pipelined architecture called fractal engine to implement the operations in FBP. Fractal engine is simple, modular, scaleable and is optimized to execute both low level and mid level operations. We note that implementation of the basic operations by fractal engine enables efficient execution of a majority of visual computing tasks. These include spatial filtering, contrast enhancement, frequency domain operations, histogram calculation, geometric transforms, indexing, vector quantization, fractal block coding, motion estimation, etc. The individual modules of fractal engine have been implemented in VHDL (VHSIC hardware description language). We have chosen to demonstrate the real-time execution capability of fractal engine by mapping a fractal block coding (FBC) algorithm onto the proposed architecture.

Citation Download Citation

Omid Fatemi and Sethuraman Panchanathan "Fractal engine", Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); https://doi.org/10.1117/12.263529

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available