Progress On A Systolic Processor Implementation

J. J. Symanski

doi:10.1117/12.933689

28 December 1982 Progress On A Systolic Processor Implementation

J. J. Symanski

Proceedings Volume 0341, Real-Time Signal Processing V; (1982) https://doi.org/10.1117/12.933689
Event: 1982 Technical Symposium East, 1982, Arlington, United States

Abstract

Parallel algorithms using systolic and wavefront processors have been proposed for a number of matrix operations important for signal processing; namely, matrix-vector multiplication, matrix multiplication/addition, linear equation solution, least squares solution via orthogonal triangular factorization, and singular value decomposition. In principle, such systolic and wavefront processors should greatly facilitate the application of VLSI/VHSIC technology to real-time signal processing by providing modular parallelism and regularity of design while requiring only local interconnects and simple timing. In order to validate proposed architectures and algorithms, a two-dimensional systolic array testbed has been designed and fabricated. The array has programmable processing elements, is dynamically reconfigurable, and will perform 16-bit and 32-bit integer and 32-bit floating point computations. The array will be used to test and evaluate algorithms and data paths for future implementation in VLSI/VHSIC technology. This paper gives a brief system overview, a description of the array hardware, and an explanation of control and data paths in the array. The software system and a matrix multiplication operation are also presented.

Citation Download Citation

J. J. Symanski "Progress On A Systolic Processor Implementation", Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); https://doi.org/10.1117/12.933689

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