FRAM technologies compatible with 0.5-um CMOS logics

Yuji Furumura; Tatsuya Yamazaki; Mitsuhiro Nakamura; Ken-ichi Inoue; Hisashi Miyazawa; Naoya Sashida; Rei Satomi; Yoshikazu Katoh; Souichirou Ozawa; Kazuaki Takai; Hideyuki Noshiro; Rika Shinohara; Yoshiroh Obata; Andrew Kerry; Kouji Tani; Sinji Nakashima; Tetsuya Nakajima; Masahiko Imai; Tohru Takesima; Toshiyuki Teramoto; Chikai Ohono; Moritaka Nakamura; Takayuki Murakami

doi:10.1117/12.323989

4 September 1998 FRAM technologies compatible with 0.5-μm CMOS logics

Yuji Furumura, Tatsuya Yamazaki, Mitsuhiro Nakamura, Ken-ichi Inoue, Hisashi Miyazawa, Naoya Sashida, Rei Satomi, Yoshikazu Katoh, Souichirou Ozawa, Kazuaki Takai, Hideyuki Noshiro, Rika Shinohara, Yoshiroh Obata, Andrew Kerry, Kouji Tani, Sinji Nakashima, Tetsuya Nakajima, Masahiko Imai, Tohru Takesima, Toshiyuki Teramoto, Chikai Ohono, Moritaka Nakamura, Takayuki Murakami

Author Affiliations +

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323989
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

We developed FRAM (FRAM is a registered trademark of Ramtron International Corporation that stands for FeRAM) technologies that are fully compatible with half-micron CMOS logic's. The technologies achieve 1T/1C FRAM cell 12.5 micrometer² in a size and 68k-FRAM embedded 8bit-MCU. The CMOS transistors work at 5V for a cell operation and 3V for a logic operation. We did not use a COB to employ a present CMOS processing, and used the local interconnect to reduce a chip size. We used the W plug to contact to deep diffusion layers through high-aspect contact holes. The CMP planarization was used to relax PZT deposition and Pt etching. To prevent the process degradation of PZT, we used single Al wiring with SOG as an interlayer dielectric. The cover dielectric was formed with plasma TEOS- CVD without SiN to prevent the process degradation at this case. The SiN cover will be indispensable in real products. These technologies achieved a cell size 6.95 X 1.8 equals 12.5 (micrometer²) for 1T/1C and 4.2 X 6.5 equals 27.3(micrometer²) for 2T/2C that are the smallest cell size in FRAM's that do not use a COB structure and a poly-plug as a storage.

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Yuji Furumura, Tatsuya Yamazaki, Mitsuhiro Nakamura, Ken-ichi Inoue, Hisashi Miyazawa, Naoya Sashida, Rei Satomi, Yoshikazu Katoh, Souichirou Ozawa, Kazuaki Takai, Hideyuki Noshiro, Rika Shinohara, Yoshiroh Obata, Andrew Kerry, Kouji Tani, Sinji Nakashima, Tetsuya Nakajima, Masahiko Imai, Tohru Takesima, Toshiyuki Teramoto, Chikai Ohono, Moritaka Nakamura, and Takayuki Murakami "FRAM technologies compatible with 0.5-μm CMOS logics", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323989

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