Paper
30 May 2000 Coprocessor architecture for MPEG-4 video object rendering
Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, Kai-Immo Wels
Author Affiliations +
Proceedings Volume 4067, Visual Communications and Image Processing 2000; (2000) https://doi.org/10.1117/12.386563
Event: Visual Communications and Image Processing 2000, 2000, Perth, Australia
Abstract
The most crucial backend algorithm of the new MPEG-4 standard is the computational expensive rendering of arbitrary shaped video objects to the final video scene. This co-processor architecture presents a solution for the scene rendering of the CCIR 601 video format with an arbitrary number of video objects. For the very high data bandwidth rate a hierarchical memory concept has been implemented. The total size of all rendered objects for one scene may reach two times the size of the CCIR 601 format. Running at 100 MHz clock frequency, the co-processor achieves a peak performance at about two billion multiply- accumulate operations. The co-processor has been designed for a 0.35 micrometers CMOS technology. About 60% of the overall area of 52 mm2 is used for on-chip static memory. The power consumption of the co-processor has been estimated with 1 W.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christoph Heer, Carolina Miro, Anne Lafage, Mladen Berekovic, Giovanni Ghigo, Thorsten Selinger, and Kai-Immo Wels "Coprocessor architecture for MPEG-4 video object rendering", Proc. SPIE 4067, Visual Communications and Image Processing 2000, (30 May 2000); https://doi.org/10.1117/12.386563
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KEYWORDS
Video

Clocks

Video processing

Image processing

Data processing

Image filtering

Video compression

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