Paper
20 October 2000 Corner rounding and line-end shortening in optical lithography
Author Affiliations +
Proceedings Volume 4226, Microlithographic Techniques in Integrated Circuit Fabrication II; (2000) https://doi.org/10.1117/12.404843
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
Pattern infidelity of features on the wafer is critical to the functionality of a device. Among other error sources, the feature quality on the reticle is presumed to be a key contributing factor to wafer pattern fidelity. Of course, optimization of final pattern fidelity is dependent on the imaging and process of both the mask and wafer, as well as on their relationship to one another. This paper examines the key parameters used to predict the acceptable amount of corner rounding on the reticle, and to define proper metrics of reticle shape. Pattern shapes such as isolated corners, contact holes, and line ends will be examined. For line end shortening, the influence of both the imaging and the resist process is discussed.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chris A. Mack "Corner rounding and line-end shortening in optical lithography", Proc. SPIE 4226, Microlithographic Techniques in Integrated Circuit Fabrication II, (20 October 2000); https://doi.org/10.1117/12.404843
Lens.org Logo
CITATIONS
Cited by 13 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Photomasks

Semiconducting wafers

Diffraction

Reticles

Diffusion

Image processing

Critical dimension metrology

RELATED CONTENT

Process dependencies of optical proximity corrections
Proceedings of SPIE (September 14 2001)
Prediction of MEEF using a simple model and MEEF enhancement...
Proceedings of SPIE (September 05 2001)
Impact of mask errors on full chip error budgets
Proceedings of SPIE (July 26 1999)
Patterning ULSI circuits
Proceedings of SPIE (June 07 1996)

Back to Top