Paper
21 April 2003 Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC
Author Affiliations +
Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.499031
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain
Abstract
Crosstalk propagating through the silicon substrate is a serious limiting factor on the performance of advanced mixed analog-digital CMOS integrated circuits. This problem also appears in RF chips in the form of power leakage from local oscillators or power amplifiers, as well as the noise coupled from the digital baseband circuitry. Several studies have presented measurements on simple test structures to determine the best approach to minimize this leakage. Nevertheless, these studies are usually restricted to a single technology, and the consequences of applying results to other technologies are not evaluated. Also, these studies are usually performed with on-wafer samples, and thus package effects are not taken into account. However, package parasitics are an important factor in the substrate crosstalk, since they determine how much of the leakage finds a return path to external ground. In this paper, we discuss different technological approaches to increase isolation between coupled circuits. Measurements of the isolation on some test structures fabricated in a CMOS RF technology are presented. The package parasitics effect is evaluated by comparing on-wafer vs packaged samples. Measurement results are complemented with simulations of a broader range of situations.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xavier Aragones, Diego Mateo, and Olga Boric-Lubecke "Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.499031
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Cited by 3 scholarly publications.
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KEYWORDS
Semiconducting wafers

Inductance

Digital electronics

Silicon

CMOS technology

Capacitance

Manufacturing

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