Paper
21 April 2003 Switch-based interconnect architecture for future systems on chip
Partha Pratim Pande, Cristian S Grecu, Andre Ivanov, Resve A Saleh
Author Affiliations +
Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498809
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain
Abstract
System on Chip (SoC) design involves the integration of numerous heterogeneous semiconductor intellectual property (SIP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems associated with future SoC design arise from non-scalable global wire delays, failure to achieve global synchronization with a single clock, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnects. To address these problems, we conjecture the future need and practicality of a paradigm shift in SoC design methodology from a conventional, typically bus-based approach, to a network-centric approach. In replacement of global wiring, we propose a switch-based on-chip interconnection network to interconnect IP blocks. One of the challenges in an interconnection network-based SoC is sending data from one IP block to multiple destination IP blocks simultaneously, i.e., multicasting. To achieve multicasting we introduce the concept of a bit-string encoding in the addressing mechanism to communicate among IP blocks. Another major challenge in such network-based SoCs is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To incorporate the concept of multicasting and virtual channels the silicon area consumed by the switches will increase, but that can be made to be very small in a billion-transistor SoC.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Partha Pratim Pande, Cristian S Grecu, Andre Ivanov, and Resve A Saleh "Switch-based interconnect architecture for future systems on chip", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498809
Lens.org Logo
CITATIONS
Cited by 15 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Switches

System on a chip

Computer programming

Silicon

Switching

Logic

Packet switching

RELATED CONTENT

SKIPSM implementations: morphology and much, much more
Proceedings of SPIE (October 03 1995)
1.114-gb/s time/space division switch system
Proceedings of SPIE (October 01 1990)
A High Speed Fiber Optic Switched Network
Proceedings of SPIE (January 23 1990)
Reconfiguring an FPGA-based RISC for LNS arithmetic
Proceedings of SPIE (July 24 2001)
A Survey Of Floating-Point Arithmetic Implementations
Proceedings of SPIE (November 28 1983)

Back to Top