Design and analysis of real-time wavefront processor

Luchun Zhou; Chunhong Wang; Mei Li; Wenhan Jiang

doi:10.1117/12.580431

23 December 2004 Design and analysis of real-time wavefront processor

Luchun Zhou, Chunhong Wang, Mei Li, Wenhan Jiang

Proceedings Volume 5639, Adaptive Optics and Applications III; (2004) https://doi.org/10.1117/12.580431
Event: Photonics Asia, 2004, Beijing, China

Abstract

Latency of wavefront processor is an important factor of closed loop adaptive optical systems. For an adaptive optical system using Shack-Hartmann wave-front sensing and point beam, by ways of task queue, subtask arithmetic decomposition and subtask structure design, a multi-processors structure based on moder parallelism theory is built to realize a pipeline of wavefront gradient, wavefront reconstruction and wavefront control. By traits of field programmable gate array(FPGA) and digital signal processor(DSP), a pipeline wavefront processor based on FPGA+DSP structure is built with highly real-time performance. Clocks of FPGA and DSP, “age” of correctors are primary sources of this wavefront processor’s latency. For a 61-element adaptive optical system whose sampling frequency is 2900HZ, latency of this wavefront processor is less than 100us.

Citation Download Citation

Luchun Zhou, Chunhong Wang, Mei Li, and Wenhan Jiang "Design and analysis of real-time wavefront processor", Proc. SPIE 5639, Adaptive Optics and Applications III, (23 December 2004); https://doi.org/10.1117/12.580431

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