Paper
4 May 2005 Process optimization of developer soluble organic BARC and its characteristics in CMOS devices
Yeon Hwa Lim, Young Keun Kim, Jae Sung Choi, Jeong Gun Lee
Author Affiliations +
Abstract
As the IC industry is moving toward 90nm node or below, the critical dimension size of implant layers has shrunk to 250nm or smaller. To achieve better CD uniformity, dyed KrF resist and top anti-reflective coating (TARC) are commonly used in advanced photo process of implant layers, while typical organic BARC are not used because it requires dry etch process that damages the substrate and needs additional process steps. In order to overcome those shortcomings, developable BARC is introduced. It is a new type of BARC which is soluble to developer, TMAH solution, in the resist development step. This developer-soluble KrF BARC consists of polyamic acid and its solubility to alkaline could be adjusted by changing bake condition. In this experiment, we evaluated the margin of developable BARC process. Developable BARC reduces the standing wave of photoresist and improves the ID bias and CD uniformity as applied to implant feature printing. However, Developable BARC has a narrow thermal process margin. It is the profile of developable BARC that easily changes according to the coating thickness or thermal process conditions. Even in the same bake conditions, developable BARC profile changes according to the pattern densities. To observe the effects of developable BARC on the device performance, we compare electrical data of devices produced with and without developable BARC. They have the differences in the threshold voltage, leakage current and saturation current. Probably, the residues of the developable BARC after the development bring about the differences.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yeon Hwa Lim, Young Keun Kim, Jae Sung Choi, and Jeong Gun Lee "Process optimization of developer soluble organic BARC and its characteristics in CMOS devices", Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); https://doi.org/10.1117/12.600437
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Cited by 7 scholarly publications.
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KEYWORDS
Photoresist developing

Critical dimension metrology

Semiconducting wafers

Photoresist materials

Photoresist processing

CMOS devices

Plasma etching

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