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28 June 2005 Resist baking conversion from wafers to mask-substrates
Hideo Kobayashi
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Proceedings Volume 5853, Photomask and Next-Generation Lithography Mask Technology XII; (2005) https://doi.org/10.1117/12.617090
Event: Photomask and Next Generation Lithography Mask Technology XII, 2005, Yokohama, Japan
Abstract
Resist designing for mask-making has been carried out basically using Si-wafers or chrome-coated Si-wafers, and its baking has been done for 60 to 90 seconds which was used for the wafers generally. There is a definite difference that 6025 mask-substrates (6025s) require 7.5 minutes or over to achieve 150deg.C and such, depending on a baking system configuration though, while the wafers require only 30 seconds or less, due to differences in thermal properties and in thickness between the two substrates. Resist baking conversion, by the way, is generally accomplished by adjusting the 6025s surface temperature to the wafers. Meanwhile, resist baking conversion in time, including ramping up and cooling down speed (or slope), seems not to be considered carefully between the two substrates so far. Recently, we experienced a difficulty that an essential performance of a newly designed trial resist of a low activation energy type CAR, which had been designed and developed using the wafers as usual, was not shown on the 6025s due to deteriorating in contrast, i.e. gamma value as well as remaining resist thickness in un-exposed area (dark erosion). This seemed to be due to a particular long baking for 10min. This report describes a trial and its results to convert the baking condition from the wafers to the 6025 mask-substrates, and also brings up some issues found in the resist baking conversion or adjustment.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Hideo Kobayashi "Resist baking conversion from wafers to mask-substrates", Proc. SPIE 5853, Photomask and Next-Generation Lithography Mask Technology XII, (28 June 2005); https://doi.org/10.1117/12.617090
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KEYWORDS
Semiconducting wafers
Coating
Optical lithography
Standards development
Error analysis
Safety
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