A combined space-time multiplex architecture for a stacked smart sensor chip

A. Loos; M. Schmidt; A. Graupner; D. Fey; R. Schüffny

doi:10.1117/12.662287

21 April 2006 A combined space-time multiplex architecture for a stacked smart sensor chip

A. Loos, M. Schmidt, A. Graupner, D. Fey, R. Schüffny

Proceedings Volume 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration; 61850H (2006) https://doi.org/10.1117/12.662287
Event: SPIE Photonics Europe, 2006, Strasbourg, France

Abstract

We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.

Citation Download Citation

A. Loos, M. Schmidt, A. Graupner, D. Fey, and R. Schüffny "A combined space-time multiplex architecture for a stacked smart sensor chip", Proc. SPIE 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, 61850H (21 April 2006); https://doi.org/10.1117/12.662287

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