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As the minimum pitch size becomes smaller, the gate-poly critical dimension uniformity (CDU) is a critical parameter for the device performance and an important indicator of the OPC capability. From the photolithographic point of view, the root causes of increasing gate-poly CDU is due to corner rounding effects, ripples, misalignment between the gate-poly and active layers. The corner rounding effect of the gate-poly region on the active can be severe for the sub L50 device because the space between the active layer and the gate-poly layer becomes narrow.
To correct these effects caused by litho-process the advanced OPC technique and the design rule limitation should be optimized. The OPC method which can be used to improve gate-poly CDU is defined as "Litho Process-aware OPC for the Gate-Poly CDU improvement" in this paper. The pixel based simulation algorithm which gives lots of information compared to the sparse simulation algorithm is used for the OPC and ORC. The design rule for the space limitation from RX to PC is evaluated with its own litho-process model and this evaluation result has to be reflected to the design rule and the OPC recipe to manipulate the polygons is also necessary. Additionally if misalignment exists in the minimum space between the active layer and gate-poly layer during the photo process, this corner rounding effect can be more serious, so this misalignment accounted to reduce the corner rounding effect on the gate-poly CDU. The redundant field poly polygon enclosing the contact can be cut by keeping the design rule for the overlap margin between the poly layer and the contact layer. The miss-alignment effect can be considered indirectly by sizing the active layer. The OPC convergence technique is also used to reduce the ripple phenomenon close to the concave corner and line end. As a result of retargeting to accommodate a corner rounding effects, ripple effects and misalignment correction led to an improved gate-poly CDU for a sub-50nm device.
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