Paper
19 May 2008 Yield-centric layout optimization with precise quantification of lithographic yield loss
Sachiko Kobayashi, Suigen Kyoh, Koichi Kinoshita, Yukihiro Urakawa, Eiji Morifuji, Satoshi Kuramoto, Soichi Inoue
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Abstract
Continuous shrinkage of the design rule in LSI devices brings about greater difficulty in the manufacturing process. Since not only process engineers' efforts but also yield-centric layout optimization is becoming increasingly important, such optimization has recently become a focus of interest. One of the approached is lithographic hotspot modification in design data. Using lithography compliance check and a hotspot fixing system in the early stage of design, design with wider process margin can be obtained. In order to achieve higher process yield after hotspot fixing, layout should be carefully optimized to decrease pattern-dependent yield loss. Since yield value for the design will fluctuate sensitively as designed pattern are modified, pattern should be optimized based on a comprehensive consideration of yield loss covering parametric, systematic and random effects. In this work, using lithography simulation, a lithographic yield loss model is defined and applied for precise quantification of process yield loss in 45 nm logic design. Yield loss values of each cell for lithographic, parametric and random effects are estimated, and then layouts through multiple layers are optimized to decrease total yield loss. As a result, litho-yield loss is greatly improved without deteriorating total yield value. Thus, layout is obtained that reflects an awareness of overall process yield.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sachiko Kobayashi, Suigen Kyoh, Koichi Kinoshita, Yukihiro Urakawa, Eiji Morifuji, Satoshi Kuramoto, and Soichi Inoue "Yield-centric layout optimization with precise quantification of lithographic yield loss", Proc. SPIE 7028, Photomask and Next-Generation Lithography Mask Technology XV, 70280O (19 May 2008); https://doi.org/10.1117/12.793031
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Cited by 7 scholarly publications.
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KEYWORDS
Lithography

Manufacturing

Optical proximity correction

Logic

Process engineering

Semiconducting wafers

Semiconductors

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