Implementation of the high order overlay control for mass production of 40nm node logic devices

Daisuke Umeda; Mami Miyasaka; Takayuki Uchiyama

doi:10.1117/12.813378

23 March 2009 Implementation of the high order overlay control for mass production of 40nm node logic devices

Daisuke Umeda, Mami Miyasaka, Takayuki Uchiyama

Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72720H (2009) https://doi.org/10.1117/12.813378
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

To satisfy the tight budget of critical dimension, an immersion exposure process is widely applied to critical layers of the recent advanced devices to accomplish the high performance of resolution. In our 40nm node logic devices, the overlay accuracy of the critical layers (immersion to immersion) would be required to be less than 15nm (Mean+3sigma) and the one of the sub-critical layers (dry to immersion) would be required to be less than 20nm (Mean+3sigma). Furthermore, the overlay accuracy of the critical layers might be less than 10nm (Mean+3sigma) in the 32nm node logic devices. The method of improving the overlay performance should be investigated for mass production in the future. In this report, attaching weight to productivity, we selected the technique of high order process correction with machine configuration and applied it for 40 nm node production. We evaluated the overlay performance of the critical layers using 40nm process stack wafer and found that high order grid compensation was effective for reducing the process impact on the overlay accuracy. Furthermore, about the sub-critical layers, high order grid compensation was also effective for controlling the tool matching error.

Citation Download Citation

Daisuke Umeda, Mami Miyasaka, and Takayuki Uchiyama "Implementation of the high order overlay control for mass production of 40nm node logic devices", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72720H (23 March 2009); https://doi.org/10.1117/12.813378

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KEYWORDS

Overlay metrology

Semiconducting wafers

Logic devices

Error analysis

Lithography

Logic

Control systems

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