Dual port memory based parallel programmable architecture for DSP in FPGA

Wojciech M. Zabolotny

doi:10.1117/12.872828

14 September 2010 Dual port memory based parallel programmable architecture for DSP in FPGA

Wojciech M. Zabolotny

Proceedings Volume 7745, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010; 77451E (2010) https://doi.org/10.1117/12.872828
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, 2010, Wilga, Poland

Abstract

This document presents a proposal of a new architecture for implementation of Digital Signal Processing (DSP) algorithms in Field-Programmable Gate Array (FPGA). The proposed approach uses the dual port memory for fast exchange of information between the processing units implemented in the FPGA. The special, parametrized scheme of interconnections between processing units has been also proposed, which allows to synthesize DSP system with customized number of processing units. The proposed interconnections scheme provides possibility to quickly transfer the data between processing units, at reasonable consumption of routing resources. The proposed architecture has been tested in simulations, and synthesized for real FPGA chips to verify its correctness.

Citation Download Citation

Wojciech M. Zabolotny "Dual port memory based parallel programmable architecture for DSP in FPGA", Proc. SPIE 7745, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, 77451E (14 September 2010); https://doi.org/10.1117/12.872828

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