Paper
5 December 2011 VLSI implementation of multiple large template-based image matching for automatic target recognition
Author Affiliations +
Proceedings Volume 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing; 80050A (2011) https://doi.org/10.1117/12.901994
Event: Seventh International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR2011), 2011, Guilin, China
Abstract
A special designed VLSI chip for template matching fundamentally used in automatic target recognition is proposed in this paper, it adopts normalized cross correlation algorithm. Parallelism inherent in the operation is explored to reduce the huge needed external bandwidth. As much as 8 large binary templates could be configured into four operation modes of eight 1-bit, four 2-bit, two 4-bit and one 8-bit templates using partial product scheme and they are processed in parallel. It takes 13.23ms to execute 120x160 template matching with 256x320 image, therefore is suitable for real-time applications. The prototype of the chip is emulated on FPGA and also synthesized with Design Compiler, die area is 3mm x 3.1mm and power consumption is 114.1 mw when operate at 108 MHz.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hongshi Sang, Dingbin Liao, and Yajing Yuan "VLSI implementation of multiple large template-based image matching for automatic target recognition", Proc. SPIE 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing, 80050A (5 December 2011); https://doi.org/10.1117/12.901994
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Cited by 2 scholarly publications.
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KEYWORDS
Image processing

Very large scale integration

Automatic target recognition

Digital signal processing

Binary data

Field programmable gate arrays

Signal processing

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