Pitch-based pattern splitting for 1D layout

Ryo Nakayama; Hiroyuki Ishii; Koji Mikami; Koichiro Tsujita; Hidetami Yaegashi; Kenichi Oyama; Michael C. Smayling; Valery Axelrad

doi:10.1117/12.2192529

9 July 2015 Pitch-based pattern splitting for 1D layout

Ryo Nakayama, Hiroyuki Ishii, Koji Mikami, Koichiro Tsujita, Hidetami Yaegashi, Kenichi Oyama, Michael C. Smayling, Valery Axelrad

Author Affiliations +

Proceedings Volume 9658, Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII; 96580A (2015) https://doi.org/10.1117/12.2192529
Event: Photomask Japan 2015, 2015, Yokohama, Japan

Abstract

The pattern splitting algorithm for 1D Gridded-Design-Rules layout (1D layout) for sub-10 nm node logic devices is shown. It is performed with integer linear programming (ILP) based on the conflict graph created from a grid map for each designated pitch. The relation between the number of times for patterning and the minimum pitch is shown systematically with a sample pattern of contact layer for each node. From the result, the number of times for patterning for 1D layout is fewer than that for conventional 2D layout. Moreover, an experimental result including SMO and total integrated process with hole repair technique is presented with the sample pattern of contact layer whose pattern density is relatively high among critical layers (fin, gate, local interconnect, contact, and metal).

Citation Download Citation

Ryo Nakayama, Hiroyuki Ishii, Koji Mikami, Koichiro Tsujita, Hidetami Yaegashi, Kenichi Oyama, Michael C. Smayling, and Valery Axelrad "Pitch-based pattern splitting for 1D layout", Proc. SPIE 9658, Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII, 96580A (9 July 2015); https://doi.org/10.1117/12.2192529

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