Fault Tolerance Techniques For Systolic Arrays

Franklin T. Luk; Eric K. Torng

doi:10.1117/12.942043

25 November 1987 Fault Tolerance Techniques For Systolic Arrays

Franklin T. Luk, Eric K. Torng

Proceedings Volume 0827, Real-Time Signal Processing X; (1987) https://doi.org/10.1117/12.942043
Event: 31st Annual Technical Symposium on Optical and Optoelectronic Applied Sciences and Engineering, 1987, San Diego, CA, United States

Abstract

In this paper, we study three fault tolerance techniques: data redundancy, algorithm-based fault tolerance, and pair and spare. These techniques, each individually useful, produce excitingly high levels of protection at a relatively low cost when used in combination. We first discuss the techniques separately, extending triple data redundancy to band matrix multiplication while applying algorithm-based fault tolerance to dense matrix multiplication. We then combine double data redundancy and algorithm-based fault tolerance to produce a linear array that corrects transient errors at minimal costs. Finally, we show how the above techniques can be used to implement pair and spare at half the normal cost.

Citation Download Citation

Franklin T. Luk and Eric K. Torng "Fault Tolerance Techniques For Systolic Arrays", Proc. SPIE 0827, Real-Time Signal Processing X, (25 November 1987); https://doi.org/10.1117/12.942043

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