Integration via 3rd dimension: 3D power scaling

Paolo A. Gargini

doi:10.1117/12.2501283

3 October 2018 Integration via 3rd dimension: 3D power scaling

Paolo A. Gargini

Proceedings Volume 10809, International Conference on Extreme Ultraviolet Lithography 2018; 1080914 (2018) https://doi.org/10.1117/12.2501283
Event: SPIE Photomask Technology + Extreme Ultraviolet Lithography, 2018, Monterey, California, United States

Abstract

“Geometrical Scaling” of MOS transistors supported the growth of the electronics industry for over 25 years (1975~2000) in accordance with Moore’s Law. The NTRS identified in the mid-90s major upcoming material and structural limitations of the silicon-gate transistor. To solve these problems the ITRS was formed in 1998 and the concepts of strained silicon, high-κ/metal gate, FinFET, and introduction of other semiconductor materials under “Equivalent Scaling” were identified as possible solutions to overcome these limitations. By 2011 all these new innovative technologies had been introduced into manufacturing. This approach has giving the semiconductor industry another 25 years (2000~2025) of growth. Realization of continuously smaller horizontal (2D) features will reach fundamental limits by ~2025. Flash producers have already transformed the realization of transistors from the horizontal dimension to the vertical dimension to solve this problem. Logic producers will follow. IRDS assessed that “3D Power Scaling” will extend Moore’s Law for at least another 15 years (2025~2040). How would implementation of 3D transistor and circuit affect lithographic requirements?

Conference Presentation

Citation Download Citation

Paolo A. Gargini "Integration via 3rd dimension: 3D power scaling", Proc. SPIE 10809, International Conference on Extreme Ultraviolet Lithography 2018, 1080914 (3 October 2018); https://doi.org/10.1117/12.2501283

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