Reduce probability of wafer intra-field process (printing) defects for logic and DRAM applications

Yael Sufrin; Avi Cohen; Ofir Sharoni; Rolf Seltmann

doi:10.1117/12.2535686

29 August 2019 Reduce probability of wafer intra-field process (printing) defects for logic and DRAM applications

Yael Sufrin, Avi Cohen, Ofir Sharoni, Rolf Seltmann

Proceedings Volume 11177, 35th European Mask and Lithography Conference (EMLC 2019); 1117712 (2019) https://doi.org/10.1117/12.2535686
Event: 35th European Mask and Lithography Conference, 2019, Dresden, Germany

Abstract

Wafer Intra-Field Process (Printing) Defects created due to various process segments. Narrow Lithography process window (Litho PW), effected by Dose & Focus (calibrated by FEM – Focus Exposure Matrix), is one of the major contributors for the wafer intra-filed process defects caused by hot spots. The Litho PW can be expanded by controlling the Dose parameters over the wafer intra-field. Dose parameters effect the Critical Dimension Uniformity (CDU). Controlling the wafer intra-field CDU will expand the Litho PW and will reduce the process (printing) defects. The extension of 193nm based lithography usage combined with design shrinkage rules for process control (in particular the wafer level CDU control), are extremely important and challenging task in IC manufacturing. This work will show the ZEISS CDC application (CD Control) and its significant positive effect on the intra-field CDU, Litho PW, and process defects probability, as well as introduction for wafer FAB integration flow. It will also challenge some existing process parameters specifications and will explain why IC manufacturing failures come real although all individual process parameters in spec. Specification limits for each individual parameter do not necessarily guarantee a successful process, as it’s almost impossible to anticipate and verify all possible interdependencies among different parameters. The goal is therefore, to show how to improve IC process by shrinking its individual parameters distributions, even if the variability of those parameters is in specification. This work will offer solution named as “Excursion Prevention” - Improve wafer intra-field CDU by using the ZEISS CDC tool, to reduce the wafer intra-field printing defects caused by narrow Litho PW.

Citation Download Citation

Yael Sufrin, Avi Cohen, Ofir Sharoni, and Rolf Seltmann "Reduce probability of wafer intra-field process (printing) defects for logic and DRAM applications", Proc. SPIE 11177, 35th European Mask and Lithography Conference (EMLC 2019), 1117712 (29 August 2019); https://doi.org/10.1117/12.2535686

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